AArch64FalkorHWPFFix.cpp Source File (original) (raw)

49#include

50#include

52using namespace llvm;

54#define DEBUG_TYPE "aarch64-falkor-hwpf-fix"

56 STATISTIC(NumStridedLoadsMarked, "Number of strided loads marked");

58 "Number of HW prefetch tag collisions avoided");

60 "Number of HW prefetch tag collisions not avoided due to lack of registers");

62 "Controls which tag collisions are avoided");

64namespace {

66class FalkorMarkStridedAccesses {

67public:

69 : LI(LI), SE(SE) {}

71 bool run();

73private:

74 bool runOnLoop(Loop &L);

78};

80class FalkorMarkStridedAccessesLegacy : public FunctionPass {

81public:

82 static char ID;

84 FalkorMarkStridedAccessesLegacy() : FunctionPass(ID) {

87 }

96 }

99};

100

101}

102

103char FalkorMarkStridedAccessesLegacy::ID = 0;

104

106 "Falkor HW Prefetch Fix", false, false)

112

114 return new FalkorMarkStridedAccessesLegacy();

115}

116

117bool FalkorMarkStridedAccessesLegacy::runOnFunction(Function &F) {

121 if (ST->getProcFamily() != AArch64Subtarget::Falkor)

122 return false;

123

124 if (skipFunction(F))

125 return false;

126

127 LoopInfo &LI = getAnalysis().getLoopInfo();

128 ScalarEvolution &SE = getAnalysis().getSE();

129

130 FalkorMarkStridedAccesses LDP(LI, SE);

131 return LDP.run();

132}

133

134bool FalkorMarkStridedAccesses::run() {

135 bool MadeChange = false;

136

137 for (Loop *L : LI)

139 MadeChange |= runOnLoop(*LIt);

140

141 return MadeChange;

142}

143

144bool FalkorMarkStridedAccesses::runOnLoop(Loop &L) {

145

146 if (.isInnermost())

147 return false;

148

149 bool MadeChange = false;

150

153 LoadInst *LoadI = dyn_cast(&I);

154 if (!LoadI)

155 continue;

156

158 if (L.isLoopInvariant(PtrValue))

159 continue;

160

161 const SCEV *LSCEV = SE.getSCEV(PtrValue);

162 const SCEVAddRecExpr *LSCEVAddRec = dyn_cast(LSCEV);

163 if (!LSCEVAddRec || !LSCEVAddRec->isAffine())

164 continue;

165

168 ++NumStridedLoadsMarked;

169 LLVM_DEBUG(dbgs() << "Load: " << I << " marked as strided\n");

170 MadeChange = true;

171 }

172 }

173

174 return MadeChange;

175}

176

177namespace {

178

180public:

181 static char ID;

182

185 }

186

188

193 }

194

197 MachineFunctionProperties::Property::NoVRegs);

198 }

199

200private:

202

207};

208

209

212

215 int BaseRegIdx = -1;

217 bool IsPrePost = false;

218};

219

220}

221

222char FalkorHWPFFix::ID = 0;

223

225 "Falkor HW Prefetch Fix Late Phase", false, false)

229

231 return (Dest & 0xf) | ((Base & 0xf) << 4) | ((Offset & 0x3f) << 8);

232}

233

235 int DestRegIdx;

236 int BaseRegIdx;

237 int OffsetIdx;

238 bool IsPrePost;

239

240 switch (MI.getOpcode()) {

241 default:

242 return std::nullopt;

243

244 case AArch64::LD1i64:

245 case AArch64::LD2i64:

246 DestRegIdx = 0;

247 BaseRegIdx = 3;

248 OffsetIdx = -1;

249 IsPrePost = false;

250 break;

251

252 case AArch64::LD1i8:

253 case AArch64::LD1i16:

254 case AArch64::LD1i32:

255 case AArch64::LD2i8:

256 case AArch64::LD2i16:

257 case AArch64::LD2i32:

258 case AArch64::LD3i8:

259 case AArch64::LD3i16:

260 case AArch64::LD3i32:

261 case AArch64::LD3i64:

262 case AArch64::LD4i8:

263 case AArch64::LD4i16:

264 case AArch64::LD4i32:

265 case AArch64::LD4i64:

266 DestRegIdx = -1;

267 BaseRegIdx = 3;

268 OffsetIdx = -1;

269 IsPrePost = false;

270 break;

271

272 case AArch64::LD1Onev1d:

273 case AArch64::LD1Onev2s:

274 case AArch64::LD1Onev4h:

275 case AArch64::LD1Onev8b:

276 case AArch64::LD1Onev2d:

277 case AArch64::LD1Onev4s:

278 case AArch64::LD1Onev8h:

279 case AArch64::LD1Onev16b:

280 case AArch64::LD1Rv1d:

281 case AArch64::LD1Rv2s:

282 case AArch64::LD1Rv4h:

283 case AArch64::LD1Rv8b:

284 case AArch64::LD1Rv2d:

285 case AArch64::LD1Rv4s:

286 case AArch64::LD1Rv8h:

287 case AArch64::LD1Rv16b:

288 DestRegIdx = 0;

289 BaseRegIdx = 1;

290 OffsetIdx = -1;

291 IsPrePost = false;

292 break;

293

294 case AArch64::LD1Twov1d:

295 case AArch64::LD1Twov2s:

296 case AArch64::LD1Twov4h:

297 case AArch64::LD1Twov8b:

298 case AArch64::LD1Twov2d:

299 case AArch64::LD1Twov4s:

300 case AArch64::LD1Twov8h:

301 case AArch64::LD1Twov16b:

302 case AArch64::LD1Threev1d:

303 case AArch64::LD1Threev2s:

304 case AArch64::LD1Threev4h:

305 case AArch64::LD1Threev8b:

306 case AArch64::LD1Threev2d:

307 case AArch64::LD1Threev4s:

308 case AArch64::LD1Threev8h:

309 case AArch64::LD1Threev16b:

310 case AArch64::LD1Fourv1d:

311 case AArch64::LD1Fourv2s:

312 case AArch64::LD1Fourv4h:

313 case AArch64::LD1Fourv8b:

314 case AArch64::LD1Fourv2d:

315 case AArch64::LD1Fourv4s:

316 case AArch64::LD1Fourv8h:

317 case AArch64::LD1Fourv16b:

318 case AArch64::LD2Twov2s:

319 case AArch64::LD2Twov4s:

320 case AArch64::LD2Twov8b:

321 case AArch64::LD2Twov2d:

322 case AArch64::LD2Twov4h:

323 case AArch64::LD2Twov8h:

324 case AArch64::LD2Twov16b:

325 case AArch64::LD2Rv1d:

326 case AArch64::LD2Rv2s:

327 case AArch64::LD2Rv4s:

328 case AArch64::LD2Rv8b:

329 case AArch64::LD2Rv2d:

330 case AArch64::LD2Rv4h:

331 case AArch64::LD2Rv8h:

332 case AArch64::LD2Rv16b:

333 case AArch64::LD3Threev2s:

334 case AArch64::LD3Threev4h:

335 case AArch64::LD3Threev8b:

336 case AArch64::LD3Threev2d:

337 case AArch64::LD3Threev4s:

338 case AArch64::LD3Threev8h:

339 case AArch64::LD3Threev16b:

340 case AArch64::LD3Rv1d:

341 case AArch64::LD3Rv2s:

342 case AArch64::LD3Rv4h:

343 case AArch64::LD3Rv8b:

344 case AArch64::LD3Rv2d:

345 case AArch64::LD3Rv4s:

346 case AArch64::LD3Rv8h:

347 case AArch64::LD3Rv16b:

348 case AArch64::LD4Fourv2s:

349 case AArch64::LD4Fourv4h:

350 case AArch64::LD4Fourv8b:

351 case AArch64::LD4Fourv2d:

352 case AArch64::LD4Fourv4s:

353 case AArch64::LD4Fourv8h:

354 case AArch64::LD4Fourv16b:

355 case AArch64::LD4Rv1d:

356 case AArch64::LD4Rv2s:

357 case AArch64::LD4Rv4h:

358 case AArch64::LD4Rv8b:

359 case AArch64::LD4Rv2d:

360 case AArch64::LD4Rv4s:

361 case AArch64::LD4Rv8h:

362 case AArch64::LD4Rv16b:

363 DestRegIdx = -1;

364 BaseRegIdx = 1;

365 OffsetIdx = -1;

366 IsPrePost = false;

367 break;

368

369 case AArch64::LD1i64_POST:

370 case AArch64::LD2i64_POST:

371 DestRegIdx = 1;

372 BaseRegIdx = 4;

373 OffsetIdx = 5;

374 IsPrePost = true;

375 break;

376

377 case AArch64::LD1i8_POST:

378 case AArch64::LD1i16_POST:

379 case AArch64::LD1i32_POST:

380 case AArch64::LD2i8_POST:

381 case AArch64::LD2i16_POST:

382 case AArch64::LD2i32_POST:

383 case AArch64::LD3i8_POST:

384 case AArch64::LD3i16_POST:

385 case AArch64::LD3i32_POST:

386 case AArch64::LD3i64_POST:

387 case AArch64::LD4i8_POST:

388 case AArch64::LD4i16_POST:

389 case AArch64::LD4i32_POST:

390 case AArch64::LD4i64_POST:

391 DestRegIdx = -1;

392 BaseRegIdx = 4;

393 OffsetIdx = 5;

394 IsPrePost = true;

395 break;

396

397 case AArch64::LD1Onev1d_POST:

398 case AArch64::LD1Onev2s_POST:

399 case AArch64::LD1Onev4h_POST:

400 case AArch64::LD1Onev8b_POST:

401 case AArch64::LD1Onev2d_POST:

402 case AArch64::LD1Onev4s_POST:

403 case AArch64::LD1Onev8h_POST:

404 case AArch64::LD1Onev16b_POST:

405 case AArch64::LD1Rv1d_POST:

406 case AArch64::LD1Rv2s_POST:

407 case AArch64::LD1Rv4h_POST:

408 case AArch64::LD1Rv8b_POST:

409 case AArch64::LD1Rv2d_POST:

410 case AArch64::LD1Rv4s_POST:

411 case AArch64::LD1Rv8h_POST:

412 case AArch64::LD1Rv16b_POST:

413 DestRegIdx = 1;

414 BaseRegIdx = 2;

415 OffsetIdx = 3;

416 IsPrePost = true;

417 break;

418

419 case AArch64::LD1Twov1d_POST:

420 case AArch64::LD1Twov2s_POST:

421 case AArch64::LD1Twov4h_POST:

422 case AArch64::LD1Twov8b_POST:

423 case AArch64::LD1Twov2d_POST:

424 case AArch64::LD1Twov4s_POST:

425 case AArch64::LD1Twov8h_POST:

426 case AArch64::LD1Twov16b_POST:

427 case AArch64::LD1Threev1d_POST:

428 case AArch64::LD1Threev2s_POST:

429 case AArch64::LD1Threev4h_POST:

430 case AArch64::LD1Threev8b_POST:

431 case AArch64::LD1Threev2d_POST:

432 case AArch64::LD1Threev4s_POST:

433 case AArch64::LD1Threev8h_POST:

434 case AArch64::LD1Threev16b_POST:

435 case AArch64::LD1Fourv1d_POST:

436 case AArch64::LD1Fourv2s_POST:

437 case AArch64::LD1Fourv4h_POST:

438 case AArch64::LD1Fourv8b_POST:

439 case AArch64::LD1Fourv2d_POST:

440 case AArch64::LD1Fourv4s_POST:

441 case AArch64::LD1Fourv8h_POST:

442 case AArch64::LD1Fourv16b_POST:

443 case AArch64::LD2Twov2s_POST:

444 case AArch64::LD2Twov4s_POST:

445 case AArch64::LD2Twov8b_POST:

446 case AArch64::LD2Twov2d_POST:

447 case AArch64::LD2Twov4h_POST:

448 case AArch64::LD2Twov8h_POST:

449 case AArch64::LD2Twov16b_POST:

450 case AArch64::LD2Rv1d_POST:

451 case AArch64::LD2Rv2s_POST:

452 case AArch64::LD2Rv4s_POST:

453 case AArch64::LD2Rv8b_POST:

454 case AArch64::LD2Rv2d_POST:

455 case AArch64::LD2Rv4h_POST:

456 case AArch64::LD2Rv8h_POST:

457 case AArch64::LD2Rv16b_POST:

458 case AArch64::LD3Threev2s_POST:

459 case AArch64::LD3Threev4h_POST:

460 case AArch64::LD3Threev8b_POST:

461 case AArch64::LD3Threev2d_POST:

462 case AArch64::LD3Threev4s_POST:

463 case AArch64::LD3Threev8h_POST:

464 case AArch64::LD3Threev16b_POST:

465 case AArch64::LD3Rv1d_POST:

466 case AArch64::LD3Rv2s_POST:

467 case AArch64::LD3Rv4h_POST:

468 case AArch64::LD3Rv8b_POST:

469 case AArch64::LD3Rv2d_POST:

470 case AArch64::LD3Rv4s_POST:

471 case AArch64::LD3Rv8h_POST:

472 case AArch64::LD3Rv16b_POST:

473 case AArch64::LD4Fourv2s_POST:

474 case AArch64::LD4Fourv4h_POST:

475 case AArch64::LD4Fourv8b_POST:

476 case AArch64::LD4Fourv2d_POST:

477 case AArch64::LD4Fourv4s_POST:

478 case AArch64::LD4Fourv8h_POST:

479 case AArch64::LD4Fourv16b_POST:

480 case AArch64::LD4Rv1d_POST:

481 case AArch64::LD4Rv2s_POST:

482 case AArch64::LD4Rv4h_POST:

483 case AArch64::LD4Rv8b_POST:

484 case AArch64::LD4Rv2d_POST:

485 case AArch64::LD4Rv4s_POST:

486 case AArch64::LD4Rv8h_POST:

487 case AArch64::LD4Rv16b_POST:

488 DestRegIdx = -1;

489 BaseRegIdx = 2;

490 OffsetIdx = 3;

491 IsPrePost = true;

492 break;

493

494 case AArch64::LDRBBroW:

495 case AArch64::LDRBBroX:

496 case AArch64::LDRBBui:

497 case AArch64::LDRBroW:

498 case AArch64::LDRBroX:

499 case AArch64::LDRBui:

500 case AArch64::LDRDl:

501 case AArch64::LDRDroW:

502 case AArch64::LDRDroX:

503 case AArch64::LDRDui:

504 case AArch64::LDRHHroW:

505 case AArch64::LDRHHroX:

506 case AArch64::LDRHHui:

507 case AArch64::LDRHroW:

508 case AArch64::LDRHroX:

509 case AArch64::LDRHui:

510 case AArch64::LDRQl:

511 case AArch64::LDRQroW:

512 case AArch64::LDRQroX:

513 case AArch64::LDRQui:

514 case AArch64::LDRSBWroW:

515 case AArch64::LDRSBWroX:

516 case AArch64::LDRSBWui:

517 case AArch64::LDRSBXroW:

518 case AArch64::LDRSBXroX:

519 case AArch64::LDRSBXui:

520 case AArch64::LDRSHWroW:

521 case AArch64::LDRSHWroX:

522 case AArch64::LDRSHWui:

523 case AArch64::LDRSHXroW:

524 case AArch64::LDRSHXroX:

525 case AArch64::LDRSHXui:

526 case AArch64::LDRSWl:

527 case AArch64::LDRSWroW:

528 case AArch64::LDRSWroX:

529 case AArch64::LDRSWui:

530 case AArch64::LDRSl:

531 case AArch64::LDRSroW:

532 case AArch64::LDRSroX:

533 case AArch64::LDRSui:

534 case AArch64::LDRWl:

535 case AArch64::LDRWroW:

536 case AArch64::LDRWroX:

537 case AArch64::LDRWui:

538 case AArch64::LDRXl:

539 case AArch64::LDRXroW:

540 case AArch64::LDRXroX:

541 case AArch64::LDRXui:

542 case AArch64::LDURBBi:

543 case AArch64::LDURBi:

544 case AArch64::LDURDi:

545 case AArch64::LDURHHi:

546 case AArch64::LDURHi:

547 case AArch64::LDURQi:

548 case AArch64::LDURSBWi:

549 case AArch64::LDURSBXi:

550 case AArch64::LDURSHWi:

551 case AArch64::LDURSHXi:

552 case AArch64::LDURSWi:

553 case AArch64::LDURSi:

554 case AArch64::LDURWi:

555 case AArch64::LDURXi:

556 DestRegIdx = 0;

557 BaseRegIdx = 1;

558 OffsetIdx = 2;

559 IsPrePost = false;

560 break;

561

562 case AArch64::LDRBBpost:

563 case AArch64::LDRBBpre:

564 case AArch64::LDRBpost:

565 case AArch64::LDRBpre:

566 case AArch64::LDRDpost:

567 case AArch64::LDRDpre:

568 case AArch64::LDRHHpost:

569 case AArch64::LDRHHpre:

570 case AArch64::LDRHpost:

571 case AArch64::LDRHpre:

572 case AArch64::LDRQpost:

573 case AArch64::LDRQpre:

574 case AArch64::LDRSBWpost:

575 case AArch64::LDRSBWpre:

576 case AArch64::LDRSBXpost:

577 case AArch64::LDRSBXpre:

578 case AArch64::LDRSHWpost:

579 case AArch64::LDRSHWpre:

580 case AArch64::LDRSHXpost:

581 case AArch64::LDRSHXpre:

582 case AArch64::LDRSWpost:

583 case AArch64::LDRSWpre:

584 case AArch64::LDRSpost:

585 case AArch64::LDRSpre:

586 case AArch64::LDRWpost:

587 case AArch64::LDRWpre:

588 case AArch64::LDRXpost:

589 case AArch64::LDRXpre:

590 DestRegIdx = 1;

591 BaseRegIdx = 2;

592 OffsetIdx = 3;

593 IsPrePost = true;

594 break;

595

596 case AArch64::LDNPDi:

597 case AArch64::LDNPQi:

598 case AArch64::LDNPSi:

599 case AArch64::LDPQi:

600 case AArch64::LDPDi:

601 case AArch64::LDPSi:

602 DestRegIdx = -1;

603 BaseRegIdx = 2;

604 OffsetIdx = 3;

605 IsPrePost = false;

606 break;

607

608 case AArch64::LDPSWi:

609 case AArch64::LDPWi:

610 case AArch64::LDPXi:

611 DestRegIdx = 0;

612 BaseRegIdx = 2;

613 OffsetIdx = 3;

614 IsPrePost = false;

615 break;

616

617 case AArch64::LDPQpost:

618 case AArch64::LDPQpre:

619 case AArch64::LDPDpost:

620 case AArch64::LDPDpre:

621 case AArch64::LDPSpost:

622 case AArch64::LDPSpre:

623 DestRegIdx = -1;

624 BaseRegIdx = 3;

625 OffsetIdx = 4;

626 IsPrePost = true;

627 break;

628

629 case AArch64::LDPSWpost:

630 case AArch64::LDPSWpre:

631 case AArch64::LDPWpost:

632 case AArch64::LDPWpre:

633 case AArch64::LDPXpost:

634 case AArch64::LDPXpre:

635 DestRegIdx = 1;

636 BaseRegIdx = 3;

637 OffsetIdx = 4;

638 IsPrePost = true;

639 break;

640 }

641

642

643 Register BaseReg = MI.getOperand(BaseRegIdx).getReg();

644 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP)

645 return std::nullopt;

646

648 LI.DestReg = DestRegIdx == -1 ? Register() : MI.getOperand(DestRegIdx).getReg();

649 LI.BaseReg = BaseReg;

650 LI.BaseRegIdx = BaseRegIdx;

651 LI.OffsetOpnd = OffsetIdx == -1 ? nullptr : &MI.getOperand(OffsetIdx);

652 LI.IsPrePost = IsPrePost;

653 return LI;

654}

655

659 unsigned Dest = LI.DestReg ? TRI->getEncodingValue(LI.DestReg) : 0;

660 unsigned Base = TRI->getEncodingValue(LI.BaseReg);

661 unsigned Off;

662 if (LI.OffsetOpnd == nullptr)

663 Off = 0;

664 else if (LI.OffsetOpnd->isGlobal() || LI.OffsetOpnd->isSymbol() ||

665 LI.OffsetOpnd->isCPI())

666 return std::nullopt;

667 else if (LI.OffsetOpnd->isReg())

668 Off = (1 << 5) | TRI->getEncodingValue(LI.OffsetOpnd->getReg());

669 else

670 Off = LI.OffsetOpnd->getImm() >> 2;

671

673}

674

676

677 TagMap.clear();

681 if (!LInfo)

682 continue;

683 std::optional Tag = getTag(TRI, MI, *LInfo);

684 if (!Tag)

685 continue;

686 TagMap[*Tag].push_back(&MI);

687 }

688

689 bool AnyCollisions = false;

690 for (auto &P : TagMap) {

691 auto Size = P.second.size();

692 if (Size > 1) {

693 for (auto *MI : P.second) {

694 if (TII->isStridedAccess(*MI)) {

695 AnyCollisions = true;

696 break;

697 }

698 }

699 }

700 if (AnyCollisions)

701 break;

702 }

703

704 if (!AnyCollisions)

705 return;

706

708

709

710

713 LR.clear();

714 LR.addLiveOuts(*MBB);

717 if ( TII ->isStridedAccess(MI))

718 continue;

719

720 std::optional OptLdI = getLoadInfo(MI);

721 if (!OptLdI)

722 continue;

724 std::optional OptOldTag = getTag(TRI, MI, LdI);

725 if (!OptOldTag)

726 continue;

727 auto &OldCollisions = TagMap[*OptOldTag];

728 if (OldCollisions.size() <= 1)

729 continue;

730

731 bool Fixed = false;

732 LLVM_DEBUG(dbgs() << "Attempting to fix tag collision: " << MI);

733

735 LLVM_DEBUG(dbgs() << "Skipping fix due to debug counter:\n " << MI);

736 continue;

737 }

738

739

740

741 for (unsigned OpI = 0, OpE = MI.getNumOperands(); OpI < OpE; ++OpI) {

742 if (OpI == static_cast<unsigned>(LdI.BaseRegIdx))

743 continue;

746 LR.addReg(MO.getReg());

747 }

748

749 for (unsigned ScratchReg : AArch64::GPR64RegClass) {

750 if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg))

751 continue;

752

754 NewLdI.BaseReg = ScratchReg;

755 unsigned NewTag = *getTag(TRI, MI, NewLdI);

756

757 if (TagMap.count(NewTag))

758 continue;

759

762

763

764

765

766

767

770 .addReg(AArch64::XZR)

774 BaseOpnd.setReg(ScratchReg);

775

776

777

778 if (LdI.IsPrePost) {

779 LLVM_DEBUG(dbgs() << "Doing post MOV of incremented reg: "

781 MI.getOperand(0).setReg(

782 ScratchReg);

784 TII->get(AArch64::ORRXrs), LdI.BaseReg)

785 .addReg(AArch64::XZR)

788 }

789

790 for (int I = 0, E = OldCollisions.size(); I != E; ++I)

791 if (OldCollisions[I] == &MI) {

792 std::swap(OldCollisions[I], OldCollisions[E - 1]);

793 OldCollisions.pop_back();

794 break;

795 }

796

797

798

799

800

801 TagMap[NewTag].push_back(&MI);

802 ++NumCollisionsAvoided;

805 break;

806 }

808 ++NumCollisionsNotAvoided;

809 }

810 }

811}

812

813bool FalkorHWPFFix::runOnMachineFunction(MachineFunction &Fn) {

815 if (ST.getProcFamily() != AArch64Subtarget::Falkor)

816 return false;

817

819 return false;

820

822 TRI = ST.getRegisterInfo();

823

824 MachineLoopInfo &LI = getAnalysis().getLI();

825

827

830

831 if (L->isInnermost())

832 runOnLoop(*L, Fn);

833

835}

836

unsigned const MachineRegisterInfo * MRI

aarch64 falkor hwpf fix Falkor HW Prefetch Fix Late static false unsigned makeTag(unsigned Dest, unsigned Base, unsigned Offset)

static std::optional< LoadInfo > getLoadInfo(const MachineInstr &MI)

aarch64 falkor hwpf fix Falkor HW Prefetch Fix Late Phase

static std::optional< unsigned > getTag(const TargetRegisterInfo *TRI, const MachineInstr &MI, const LoadInfo &LI)

aarch64 falkor hwpf fix late

#define FALKOR_STRIDED_ACCESS_MD

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file provides an implementation of debug counters.

#define DEBUG_COUNTER(VARNAME, COUNTERNAME, DESC)

This file defines the DenseMap class.

This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

Target-Independent Code Generator Pass Configuration Options pass.

Represent the analysis usage information of a pass.

AnalysisUsage & addRequired()

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

void setPreservesCFG()

This function should be called by the pass, iff they do not:

LLVM Basic Block Representation.

static bool shouldExecute(unsigned CounterName)

Legacy analysis pass which computes a DominatorTree.

FunctionPass class - This class is used to implement most global optimizations.

virtual bool runOnFunction(Function &F)=0

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass.

void setMetadata(unsigned KindID, MDNode *Node)

Set the metadata of the specified kind to the specified node.

A set of register units used to track register liveness.

An instruction for reading from memory.

Value * getPointerOperand()

The legacy pass manager's analysis pass to compute loop information.

Represents a single loop in the control flow graph.

static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)

reverse_iterator rbegin()

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

virtual MachineFunctionProperties getRequiredProperties() const

Properties which a MachineFunction may have at a given point in time.

MachineFunctionProperties & set(Property P)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

bool readsReg() const

readsReg - Returns true if this operand reads the previous value of its register.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

void setReg(Register Reg)

Change the register this operand corresponds to.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

virtual void getAnalysisUsage(AnalysisUsage &) const

getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...

Wrapper class representing virtual and physical registers.

This node represents a polynomial recurrence on the trip count of the specified loop.

bool isAffine() const

Return true if this represents an expression A + B*x where A and B are loop invariant values.

This class represents an analyzed expression in the program.

The main scalar evolution driver.

const SCEV * getSCEV(Value *V)

Return a SCEV expression for the full generality of the specified expression.

Target-Independent Code Generator Pass Configuration Options.

TMC & getTM() const

Get the right type of TargetMachine for this target.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

LLVM Value Representation.

LLVMContext & getContext() const

All values hold a context through their type.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

PointerTypeMap run(const Module &M)

Compute the PointerTypeMap for the module M.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

FunctionPass * createFalkorMarkStridedAccessesPass()

FunctionPass * createFalkorHWPFFixPass()

void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

void initializeFalkorHWPFFixPass(PassRegistry &)

iterator_range< df_iterator< T > > depth_first(const T &G)

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

A record for a potential prefetch made during the initial scan of the loop.