AArch64GlobalISelUtils.cpp Source File (original) (raw)

16using namespace llvm;

18std::optional

23 if (MI.getOpcode() != AArch64::G_DUP)

24 return std::nullopt;

25 Register Src = MI.getOperand(1).getReg();

26 if (auto ValAndVReg =

28 return RegOrConstant(ValAndVReg->Value.getSExtValue());

30}

32std::optional<int64_t>

37 return std::nullopt;

38 return Splat->getCst();

39}

54 if (!MaybeSub || MaybeSub->getOpcode() != TargetOpcode::G_SUB ||

57 return false;

58 auto MaybeZero =

60 return MaybeZero && MaybeZero->Value.getZExtValue() == 0;

61}

65 bool MinSize) {

66 assert(MI.getOpcode() == TargetOpcode::G_MEMSET);

69 if (!TLI.getLibcallName(RTLIB::BZERO))

70 return false;

71 auto Zero =

73 if (!Zero || Zero->Value.getSExtValue() != 0)

74 return false;

79 if (!MinSize) {

83 MI.getOperand(2).getReg(), MRI)) {

84 if (Size->Value.getSExtValue() <= 256)

85 return false;

86 }

87 }

90 MIRBuilder

91 .buildInstr(TargetOpcode::G_BZERO, {},

92 {MI.getOperand(0), MI.getOperand(2)})

93 .addImm(MI.getOperand(3).getImm())

95 MI.eraseFromParent();

96 return true;

97}

99std::tuple<uint16_t, Register>

104

106 if (isUInt<16>(ConstDiscVal->getZExtValue())) {

107 ConstDisc = ConstDiscVal->getZExtValue();

108 AddrDisc = AArch64::NoRegister;

109 }

110 return std::make_tuple(ConstDisc, AddrDisc);

111 }

112

114 if (!DiscMI || DiscMI->getOpcode() != TargetOpcode::G_INTRINSIC ||

116 return std::make_tuple(ConstDisc, AddrDisc);

117

118 if (auto ConstDiscVal =

120 if (isUInt<16>(ConstDiscVal->getZExtValue())) {

121 ConstDisc = ConstDiscVal->getZExtValue();

123 }

124 }

125 return std::make_tuple(ConstDisc, AddrDisc);

126}

127

132 switch (P) {

133 default:

137 break;

140 break;

143 break;

146 break;

149 break;

153 break;

156 break;

159 break;

163 break;

166 break;

169 break;

172 break;

175 break;

178 break;

181 break;

184 break;

185 }

186}

187

191 Invert = false;

192 switch (P) {

193 default:

194

196 break;

198 Invert = true;

199 [[fallthrough]];

203 break;

209

210

211 Invert = true;

213 CondCode2);

214 break;

215 }

216}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file describes how to lower LLVM code to machine code.

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

@ FCMP_OEQ

0 0 0 1 True if ordered and equal

@ FCMP_TRUE

1 1 1 1 Always true (always folded)

@ FCMP_OLT

0 1 0 0 True if ordered and less than

@ FCMP_ULE

1 1 0 1 True if unordered, less than, or equal

@ FCMP_OGT

0 0 1 0 True if ordered and greater than

@ FCMP_OGE

0 0 1 1 True if ordered and greater than or equal

@ FCMP_ULT

1 1 0 0 True if unordered or less than

@ FCMP_ONE

0 1 1 0 True if ordered and operands are unequal

@ FCMP_UEQ

1 0 0 1 True if unordered or equal

@ FCMP_UGT

1 0 1 0 True if unordered or greater than

@ FCMP_OLE

0 1 0 1 True if ordered and less than or equal

@ FCMP_ORD

0 1 1 1 True if ordered (no nans)

@ FCMP_UNE

1 1 1 0 True if unordered or not equal

@ FCMP_UGE

1 0 1 1 True if unordered, greater than, or equal

@ FCMP_FALSE

0 0 0 0 Always false (always folded)

@ FCMP_UNO

1 0 0 0 True if unordered: isnan(X) | isnan(Y)

static LLVM_ABI bool isEquality(Predicate pred)

Determine if this is an equals/not equals predicate.

Predicate getInversePredicate() const

For example, EQ -> NE, UGT -> ULE, SLT -> SGE, OEQ -> UNE, UGT -> OLE, OLT -> UGE,...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Helper class to build MachineInstr.

MachineInstrBuilder buildInstr(unsigned Opcode)

Build and insert = Opcode .

MachineFunction & getMF()

Getter for the function we currently build.

void setInstrAndDebugLoc(MachineInstr &MI)

Set the insertion point to before MI, and set the debug loc to MI's loc.

MachineRegisterInfo * getMRI()

Getter for MRI.

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

bool getFlag(MIFlag Flag) const

Return whether an MI flag is set.

const MachineOperand & getOperand(unsigned i) const

getReg - Returns the register number.

Intrinsic::ID getIntrinsicID() const

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Represents a value which can be a Register or a constant.

Wrapper class representing virtual and physical registers.

virtual const TargetLowering * getTargetLowering() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

std::tuple< uint16_t, Register > extractPtrauthBlendDiscriminators(Register Disc, MachineRegisterInfo &MRI)

Analyze a ptrauth discriminator value to try to find the constant integer and address parts,...

Definition AArch64GlobalISelUtils.cpp:100

std::optional< RegOrConstant > getAArch64VectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)

Definition AArch64GlobalISelUtils.cpp:19

void changeFCMPPredToAArch64CC(const CmpInst::Predicate P, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)

Find the AArch64 condition codes necessary to represent P for a scalar floating point comparison.

Definition AArch64GlobalISelUtils.cpp:128

bool tryEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder, bool MinSize)

Replace a G_MEMSET with a value of 0 with a G_BZERO instruction if it is supported and beneficial to ...

Definition AArch64GlobalISelUtils.cpp:63

void changeVectorFCMPPredToAArch64CC(const CmpInst::Predicate P, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert)

Find the AArch64 condition codes necessary to represent P for a vector floating point comparison.

Definition AArch64GlobalISelUtils.cpp:188

bool isCMN(const MachineInstr *MaybeSub, const CmpInst::Predicate &Pred, const MachineRegisterInfo &MRI)

Definition AArch64GlobalISelUtils.cpp:41

std::optional< int64_t > getAArch64VectorSplatScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI)

Definition AArch64GlobalISelUtils.cpp:33

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)

If VReg is defined by a G_CONSTANT, return the corresponding value.

LLVM_ABI std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)

LLVM_ABI std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)

If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

LLVM_ABI std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)

If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...