AArch64InstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H

14#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H

20#include

22#define GET_INSTRINFO_HEADER

23#include "AArch64GenInstrInfo.inc"

25namespace llvm {

27class AArch64Subtarget;

34#define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"

100

162

173

175

179};

183

184public:

186

187

188

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191

193

195

197 Register &DstReg, unsigned &SubIdx) const override;

198

199 bool

202

204 int &FrameIndex) const override;

206 int &FrameIndex) const override;

207

208

209

211 int &FrameIndex) const override;

212

213

215 int &FrameIndex) const override;

216

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304 std::optional

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321

322

323

326 int64_t &Offset, bool &OffsetIsScalable,

329

330

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337

338

339

341 int64_t &MinOffset, int64_t &MaxOffset);

342

344 int64_t Offset1, bool OffsetIsScalable1,

346 int64_t Offset2, bool OffsetIsScalable2,

347 unsigned ClusterSize,

348 unsigned NumBytes) const override;

349

352 MCRegister SrcReg, bool KillSrc, unsigned Opcode,

356 bool KillSrc, unsigned Opcode, unsigned ZeroReg,

360 bool KillSrc, bool RenamableDest = false,

361 bool RenamableSrc = false) const override;

362

367

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374

375

377

384 VirtRegMap *VRM = nullptr) const override;

385

386

387

389 int64_t BrOffset) const override;

390

392

396 int64_t BrOffset, RegScavenger *RS) const override;

397

401 bool AllowModify = false) const override;

403 MachineBranchPredicate &MBP,

404 bool AllowModify) const override;

406 int *BytesRemoved = nullptr) const override;

410 int *BytesAdded = nullptr) const override;

411

412 std::unique_ptrTargetInstrInfo::PipelinerLoopInfo

414

415 bool

419 int &) const override;

423 Register FalseReg) const override;

424

427

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434

435

436

438 Register &SrcReg2, int64_t &CmpMask,

439 int64_t &CmpValue) const override;

440

441

443 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,

446

448

449

450

452

453

454

455 bool getMachineCombinerPatterns(MachineInstr &Root,

457 bool DoRegPressureReduce) const override;

458

459

460

461 bool isAssociativeAndCommutative(const MachineInstr &Inst,

462 bool Invert) const override;

463

464

465

466 bool isAccumulationOpcode(unsigned Opcode) const override;

467

468

469 unsigned getAccumulationStartOpcode(unsigned Opcode) const override;

470

471 unsigned

472 getReduceOpcodeForAccumulator(unsigned int AccumulatorOpCode) const override;

473

474

475

476

477 void genAlternativeCodeSequence(

482

483 bool useMachineCombiner() const override;

484

485 bool expandPostRAPseudo(MachineInstr &MI) const override;

486

487 std::pair<unsigned, unsigned>

488 decomposeMachineOperandsTargetFlags(unsigned TF) const override;

490 getSerializableDirectMachineOperandTargetFlags() const override;

492 getSerializableBitmaskMachineOperandTargetFlags() const override;

494 getSerializableMachineMemOperandTargetFlags() const override;

495

497 bool OutlineFromLinkOnceODRs) const override;

498 std::optional<std::unique_ptroutliner::OutlinedFunction>

499 getOutliningCandidateInfo(

501 std::vectoroutliner::Candidate &RepeatedSequenceLocs,

502 unsigned MinRepeats) const override;

503 void mergeOutliningCandidateAttributes(

504 Function &F, std::vectoroutliner::Candidate &Candidates) const override;

507 unsigned Flags) const override;

509 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>

517 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;

518

521 bool AllowSideEffects = true) const override;

522

523

524 uint64_t getElementSizeForOpcode(unsigned Opc) const;

525

526

527

528 bool isPTestLikeOpcode(unsigned Opc) const;

529

530 bool isWhileOpcode(unsigned Opc) const;

531

532

533 static bool isFalkorShiftExtFast(const MachineInstr &MI);

534

535

537

538 std::optional isAddImmediate(const MachineInstr &MI,

540

541 bool isFunctionSafeToSplit(const MachineFunction &MF) const override;

542

544

545 std::optional

547

548 unsigned int getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;

549

550 bool isExtendLikelyToBeFolded(MachineInstr &ExtMI,

552

553 static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset,

554 int64_t &NumBytes,

555 int64_t &NumPredicateVectors,

556 int64_t &NumDataVectors);

557 static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset,

558 int64_t &ByteSized,

559 int64_t &VGSized);

560

561

562

563

564 bool isLegalAddressingMode(unsigned NumBytes, int64_t Offset,

565 unsigned Scale) const;

566

567

568

569

572 bool FrameSetup) const;

573

574#define GET_INSTRINFO_HELPER_DECLS

575#include "AArch64GenInstrInfo.inc"

576

577protected:

578

579

580

581 std::optional

583 std::optional

585

586private:

587 unsigned getInstBundleLength(const MachineInstr &MI) const;

588

589

590

591

592

593 void fixupPostOutline(MachineBasicBlock &MBB) const;

594

595 void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,

596 MachineBasicBlock *TBB,

598 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,

599 const MachineRegisterInfo &MRI) const;

600 bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,

601 int CmpValue, const MachineRegisterInfo &MRI) const;

602

603

604

605 Register findRegisterToSaveLRTo(outliner::Candidate &C) const;

606

607

608

609 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,

610 unsigned PredReg,

611 const MachineRegisterInfo *MRI) const;

612 std::optional

613 canRemovePTestInstr(MachineInstr *PTest, MachineInstr *Mask,

614 MachineInstr *Pred, const MachineRegisterInfo *MRI) const;

615

616

617 bool verifyInstruction(const MachineInstr &MI,

618 StringRef &ErrInfo) const override;

619};

620

622 bool N = false;

623 bool Z = false;

624 bool C = false;

625 bool V = false;

626

628

630 this->N |= UsedFlags.N;

631 this->Z |= UsedFlags.Z;

632 this->C |= UsedFlags.C;

633 this->V |= UsedFlags.V;

634 return *this;

635 }

636};

637

638

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642

643std::optional

645 const TargetRegisterInfo &TRI,

646 SmallVectorImpl<MachineInstr *> *CCUseInstrs = nullptr);

647

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651 const MachineInstr &UseMI,

652 const TargetRegisterInfo *TRI);

653

654MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg,

655 unsigned Reg, const StackOffset &Offset,

656 bool LastAdjustmentWasScalable = true);

657MCCFIInstruction

659 const StackOffset &OffsetFromDefCFA,

660 std::optional<int64_t> IncomingVGOffsetFromDefCFA);

661

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663

664

665

667 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,

668 StackOffset Offset, const TargetInstrInfo *TII,

670 bool SetNZCV = false, bool NeedsWinCFI = false,

671 bool *HasWinCFI = nullptr, bool EmitCFAOffset = false,

672 StackOffset InitialOffset = {},

673 unsigned FrameReg = AArch64::SP);

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704 bool *OutUseUnscaledOp = nullptr,

705 unsigned *OutUnscaledOp = nullptr,

706 int64_t *EmittableOffset = nullptr);

707

709

711 switch (Opc) {

712 case AArch64::Bcc:

713 case AArch64::CBZW:

714 case AArch64::CBZX:

715 case AArch64::CBNZW:

716 case AArch64::CBNZX:

717 case AArch64::TBZW:

718 case AArch64::TBZX:

719 case AArch64::TBNZW:

720 case AArch64::TBNZX:

721 case AArch64::CBWPri:

722 case AArch64::CBXPri:

723 case AArch64::CBBAssertExt:

724 case AArch64::CBHAssertExt:

725 case AArch64::CBWPrr:

726 case AArch64::CBXPrr:

727 return true;

728 default:

729 return false;

730 }

731}

732

734 switch (Opc) {

735 case AArch64::BR:

736 case AArch64::BRAA:

737 case AArch64::BRAB:

738 case AArch64::BRAAZ:

739 case AArch64::BRABZ:

740 return true;

741 }

742 return false;

743}

744

746 switch (Opc) {

747 case AArch64::BLR:

748 case AArch64::BLRAA:

749 case AArch64::BLRAB:

750 case AArch64::BLRAAZ:

751 case AArch64::BLRABZ:

752 return true;

753 default:

754 return false;

755 }

756}

757

759 switch (Opc) {

760 case AArch64::PTRUE_B:

761 case AArch64::PTRUE_H:

762 case AArch64::PTRUE_S:

763 case AArch64::PTRUE_D:

764 return true;

765 default:

766 return false;

767 }

768}

769

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776 switch (K) {

777 case IA: case IB: return AArch64::XPACI;

778 case DA: case DB: return AArch64::XPACD;

779 }

781}

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783

784

787 switch (K) {

788 case IA: return Zero ? AArch64::AUTIZA : AArch64::AUTIA;

789 case IB: return Zero ? AArch64::AUTIZB : AArch64::AUTIB;

790 case DA: return Zero ? AArch64::AUTDZA : AArch64::AUTDA;

791 case DB: return Zero ? AArch64::AUTDZB : AArch64::AUTDB;

792 }

794}

795

796

797

800 switch (K) {

801 case IA: return Zero ? AArch64::PACIZA : AArch64::PACIA;

802 case IB: return Zero ? AArch64::PACIZB : AArch64::PACIB;

803 case DA: return Zero ? AArch64::PACDZA : AArch64::PACDA;

804 case DB: return Zero ? AArch64::PACDZB : AArch64::PACDB;

805 }

807}

808

809

810#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X)

811#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3)

812#define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7)

813#define TSFLAG_INSTR_FLAGS(X) ((X) << 9)

814#define TSFLAG_SME_MATRIX_TYPE(X) ((X) << 11)

815

816

817namespace AArch64 {

818

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842

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864#undef TSFLAG_ELEMENT_SIZE_TYPE

865#undef TSFLAG_DESTRUCTIVE_INST_TYPE

866#undef TSFLAG_FALSE_LANE_TYPE

867#undef TSFLAG_INSTR_FLAGS

868#undef TSFLAG_SME_MATRIX_TYPE

869

873

875}

876

877}

878

879#endif

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

#define TSFLAG_DESTRUCTIVE_INST_TYPE(X)

Definition AArch64InstrInfo.h:811

#define TSFLAG_SME_MATRIX_TYPE(X)

Definition AArch64InstrInfo.h:814

#define TSFLAG_FALSE_LANE_TYPE(X)

Definition AArch64InstrInfo.h:812

#define TSFLAG_INSTR_FLAGS(X)

Definition AArch64InstrInfo.h:813

#define TSFLAG_ELEMENT_SIZE_TYPE(X)

Definition AArch64InstrInfo.h:810

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Promote Memory to Register

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

Definition AArch64InstrInfo.h:180

static bool isHForm(const MachineInstr &MI)

Returns whether the instruction is in H form (16 bit operands)

void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override

static bool hasBTISemantics(const MachineInstr &MI)

Returns whether the instruction can be compatible with non-zero BTYPE.

static bool isQForm(const MachineInstr &MI)

Returns whether the instruction is in Q form (128 bit operands)

static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, TypeSize &Width, int64_t &MinOffset, int64_t &MaxOffset)

Returns true if opcode Opc is a memory operation.

static bool isTailCallReturnInst(const MachineInstr &MI)

Returns true if MI is one of the TCRETURN* instructions.

static bool isFPRCopy(const MachineInstr &MI)

Does this instruction rename an FPR without modifying bits?

MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override

std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override

If the specific machine instruction is an instruction that moves/copies value from one register to an...

static int getMemScale(const MachineInstr &MI)

Definition AArch64InstrInfo.h:245

MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override

bool isSubregFoldable() const override

Definition AArch64InstrInfo.h:376

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

GetInstSize - Return the number of bytes of code the specified instruction may be.

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

static bool isGPRCopy(const MachineInstr &MI)

Does this instruction rename a GPR without modifying bits?

static unsigned convertToFlagSettingOpc(unsigned Opc)

Return the opcode that set flags when possible.

bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override

bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override

Check for post-frame ptr elimination stack locations as well.

static const MachineOperand & getLdStOffsetOp(const MachineInstr &MI)

Returns the immediate offset operator of a load/store.

bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override

static std::optional< unsigned > getUnscaledLdSt(unsigned Opc)

Returns the unscaled load/store for the scaled load/store opcode, if there is a corresponding unscale...

static bool hasUnscaledLdStOffset(unsigned Opc)

Return true if it has an unscaled load/store offset.

static const MachineOperand & getLdStAmountOp(const MachineInstr &MI)

Returns the shift amount operator of a load/store.

static bool hasUnscaledLdStOffset(MachineInstr &MI)

Definition AArch64InstrInfo.h:235

static bool isPreLdSt(const MachineInstr &MI)

Returns whether the instruction is a pre-indexed load/store.

std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override

bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override

bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const override

void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

static bool isPairableLdStInst(const MachineInstr &MI)

Return true if pairing the given load or store may be paired with another.

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

const AArch64RegisterInfo & getRegisterInfo() const

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

Definition AArch64InstrInfo.h:190

static bool isPreSt(const MachineInstr &MI)

Returns whether the instruction is a pre-indexed store.

MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override

void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

AArch64InstrInfo(const AArch64Subtarget &STI)

static bool isPairedLdSt(const MachineInstr &MI)

Returns whether the instruction is a paired load/store.

bool getMemOperandWithOffsetWidth(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, TypeSize &Width, const TargetRegisterInfo *TRI) const

If OffsetIsScalable is set to 'true', the offset is scaled by vscale.

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

static bool isStridedAccess(const MachineInstr &MI)

Return true if the given load or store is a strided memory access.

bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override

Detect opportunities for ldp/stp formation.

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

bool isThroughputPattern(unsigned Pattern) const override

Return true when a code sequence can improve throughput.

MachineOperand & getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const

Return the immediate offset of the base register in a load/store LdSt.

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override

bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override

static bool isLdStPairSuppressed(const MachineInstr &MI)

Return true if pairing the given load or store is hinted to be unprofitable.

Check for post-frame ptr elimination stack locations as well.

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

MachineBasicBlock::iterator probedStackAlloc(MachineBasicBlock::iterator MBBI, Register TargetReg, bool FrameSetup) const

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...

static unsigned getLoadStoreImmIdx(unsigned Opc)

Returns the index for the immediate for a given instruction.

static bool isGPRZero(const MachineInstr &MI)

Does this instruction set its full destination register to zero?

void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2,...

CombinerObjective getCombinerObjective(unsigned Pattern) const override

static bool isFpOrNEON(Register Reg)

Returns whether the physical register is FP or NEON.

bool isAsCheapAsAMove(const MachineInstr &MI) const override

std::optional< DestSourcePair > isCopyLikeInstrImpl(const MachineInstr &MI) const override

static void suppressLdStPair(MachineInstr &MI)

Hint that pairing the given load or store is unprofitable.

static bool isPreLd(const MachineInstr &MI)

Returns whether the instruction is a pre-indexed load.

void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const

bool optimizeCondBranch(MachineInstr &MI) const override

Replace csincr-branch sequence by simple conditional branch.

static int getMemScale(unsigned Opc)

Scaling factor for (scaled or unscaled) load or store.

bool isCandidateToMergeOrPair(const MachineInstr &MI) const

Return true if this is a load/store that can be potentially paired/merged.

MCInst getNop() const override

static const MachineOperand & getLdStBaseOp(const MachineInstr &MI)

Returns the base register operator of a load/store.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Instances of this class represent a single low-level machine instruction.

Wrapper class representing physical registers. Should be passed by value.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

Flags

Flags values. These may be or'd together.

This class contains meta information specific to a module.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StackOffset holds a fixed and a scalable offset in bytes.

virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const

Target-dependent implementation for foldMemoryOperand.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

int getSVERevInstr(uint16_t Opcode)

FalseLaneType

Definition AArch64InstrInfo.h:843

@ FalseLanesZero

Definition AArch64InstrInfo.h:845

@ FalseLanesMask

Definition AArch64InstrInfo.h:844

@ FalseLanesUndef

Definition AArch64InstrInfo.h:846

int getSMEPseudoMap(uint16_t Opcode)

ElementSizeType

Definition AArch64InstrInfo.h:819

@ ElementSizeD

Definition AArch64InstrInfo.h:825

@ ElementSizeNone

Definition AArch64InstrInfo.h:821

@ ElementSizeS

Definition AArch64InstrInfo.h:824

@ ElementSizeB

Definition AArch64InstrInfo.h:822

@ ElementSizeH

Definition AArch64InstrInfo.h:823

@ ElementSizeMask

Definition AArch64InstrInfo.h:820

static const uint64_t InstrFlagIsWhile

Definition AArch64InstrInfo.h:850

static const uint64_t InstrFlagIsPTestLike

Definition AArch64InstrInfo.h:851

DestructiveInstType

Definition AArch64InstrInfo.h:828

@ DestructiveOther

Definition AArch64InstrInfo.h:831

@ Destructive2xRegImmUnpred

Definition AArch64InstrInfo.h:839

@ DestructiveBinaryShImmUnpred

Definition AArch64InstrInfo.h:834

@ DestructiveUnary

Definition AArch64InstrInfo.h:832

@ DestructiveInstTypeMask

Definition AArch64InstrInfo.h:829

@ DestructiveBinaryImm

Definition AArch64InstrInfo.h:833

@ DestructiveBinary

Definition AArch64InstrInfo.h:835

@ DestructiveUnaryPassthru

Definition AArch64InstrInfo.h:840

@ DestructiveBinaryComm

Definition AArch64InstrInfo.h:836

@ DestructiveTernaryCommWithRev

Definition AArch64InstrInfo.h:838

@ NotDestructive

Definition AArch64InstrInfo.h:830

@ DestructiveBinaryCommWithRev

Definition AArch64InstrInfo.h:837

SMEMatrixType

Definition AArch64InstrInfo.h:853

@ SMEMatrixTileD

Definition AArch64InstrInfo.h:859

@ SMEMatrixTileB

Definition AArch64InstrInfo.h:856

@ SMEMatrixNone

Definition AArch64InstrInfo.h:855

@ SMEMatrixTileQ

Definition AArch64InstrInfo.h:860

@ SMEMatrixArray

Definition AArch64InstrInfo.h:861

@ SMEMatrixTileS

Definition AArch64InstrInfo.h:858

@ SMEMatrixTileH

Definition AArch64InstrInfo.h:857

@ SMEMatrixTypeMask

Definition AArch64InstrInfo.h:854

int getSVEPseudoMap(uint16_t Opcode)

int getSVENonRevInstr(uint16_t Opcode)

@ C

The default llvm calling convention, compatible with C.

InstrType

Represents how an instruction should be mapped by the outliner.

This is an optimization pass for GlobalISel generic memory operations.

static bool isCondBranchOpcode(int Opc)

Definition AArch64InstrInfo.h:710

MCCFIInstruction createDefCFA(const TargetRegisterInfo &TRI, unsigned FrameReg, unsigned Reg, const StackOffset &Offset, bool LastAdjustmentWasScalable=true)

static bool isPTrueOpcode(unsigned Opc)

Definition AArch64InstrInfo.h:758

int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int64_t *EmittableOffset=nullptr)

Check if the Offset is a valid frame offset for MI.

static bool isIndirectBranchOpcode(int Opc)

Definition AArch64InstrInfo.h:733

static unsigned getXPACOpcodeForKey(AArch64PACKey::ID K)

Return XPAC opcode to be used for a ptrauth strip using the given key.

Definition AArch64InstrInfo.h:774

unsigned getBLRCallOpcode(const MachineFunction &MF)

Return opcode to be used for indirect calls.

AArch64FrameOffsetStatus

Use to report the frame offset status in isAArch64FrameOffsetLegal.

Definition AArch64InstrInfo.h:683

@ AArch64FrameOffsetIsLegal

Offset is legal.

Definition AArch64InstrInfo.h:685

@ AArch64FrameOffsetCanUpdate

Offset can apply, at least partly.

Definition AArch64InstrInfo.h:686

@ AArch64FrameOffsetCannotUpdate

Offset cannot apply.

Definition AArch64InstrInfo.h:684

static bool isSEHInstruction(const MachineInstr &MI)

static bool isIndirectCallOpcode(unsigned Opc)

Definition AArch64InstrInfo.h:745

AArch64MachineCombinerPattern

Definition AArch64InstrInfo.h:37

@ MULSUBv8i16_OP2

Definition AArch64InstrInfo.h:76

@ GATHER_LANE_i16

Definition AArch64InstrInfo.h:177

@ MULSUBW_OP1

Definition AArch64InstrInfo.h:45

@ FMLAv2f64_OP2

Definition AArch64InstrInfo.h:127

@ FMULv4i16_indexed_OP1

Definition AArch64InstrInfo.h:167

@ FMLSv1i32_indexed_OP2

Definition AArch64InstrInfo.h:140

@ MULSUBv2i32_indexed_OP1

Definition AArch64InstrInfo.h:95

@ MULADDXI_OP1

Definition AArch64InstrInfo.h:53

@ FMULSUBS_OP2

Definition AArch64InstrInfo.h:108

@ FMLAv2i32_indexed_OP2

Definition AArch64InstrInfo.h:133

@ FNMULSUBS_OP1

Definition AArch64InstrInfo.h:114

@ MULADDv4i16_indexed_OP2

Definition AArch64InstrInfo.h:83

@ FMLAv1i64_indexed_OP1

Definition AArch64InstrInfo.h:118

@ MULSUBv16i8_OP1

Definition AArch64InstrInfo.h:71

@ FMLAv8i16_indexed_OP2

Definition AArch64InstrInfo.h:131

@ FMULADDH_OP1

Definition AArch64InstrInfo.h:101

@ FMULv2i32_indexed_OP1

Definition AArch64InstrInfo.h:163

@ MULSUBv8i16_indexed_OP2

Definition AArch64InstrInfo.h:94

@ FMLSv4f16_OP2

Definition AArch64InstrInfo.h:143

@ FMLSv2f32_OP1

Definition AArch64InstrInfo.h:146

@ FNMULSUBH_OP1

Definition AArch64InstrInfo.h:113

@ FMLAv1i64_indexed_OP2

Definition AArch64InstrInfo.h:119

@ MULSUBv4i16_indexed_OP2

Definition AArch64InstrInfo.h:92

@ FMLSv2f32_OP2

Definition AArch64InstrInfo.h:147

@ FMLAv1i32_indexed_OP1

Definition AArch64InstrInfo.h:116

@ FMLAv2i64_indexed_OP2

Definition AArch64InstrInfo.h:135

@ FMLAv2f64_OP1

Definition AArch64InstrInfo.h:126

@ FMLSv8i16_indexed_OP1

Definition AArch64InstrInfo.h:152

@ MULSUBv2i32_OP1

Definition AArch64InstrInfo.h:77

@ FMULv4i16_indexed_OP2

Definition AArch64InstrInfo.h:168

@ MULADDX_OP1

Definition AArch64InstrInfo.h:49

@ SUBADD_OP1

Definition AArch64InstrInfo.h:39

@ MULSUBv4i32_indexed_OP2

Definition AArch64InstrInfo.h:98

@ FMULv2i64_indexed_OP2

Definition AArch64InstrInfo.h:166

@ FNMADD

Definition AArch64InstrInfo.h:174

@ MULSUBXI_OP1

Definition AArch64InstrInfo.h:54

@ FMULSUBD_OP2

Definition AArch64InstrInfo.h:112

@ FMLAv4i32_indexed_OP1

Definition AArch64InstrInfo.h:138

@ FMLAv8f16_OP1

Definition AArch64InstrInfo.h:122

@ MULADDWI_OP1

Definition AArch64InstrInfo.h:47

@ MULADDv4i16_OP2

Definition AArch64InstrInfo.h:61

@ FMULSUBH_OP2

Definition AArch64InstrInfo.h:104

@ FMULv8i16_indexed_OP2

Definition AArch64InstrInfo.h:172

@ MULSUBv4i16_OP1

Definition AArch64InstrInfo.h:73

@ FMULSUBD_OP1

Definition AArch64InstrInfo.h:111

@ FMLSv2f64_OP2

Definition AArch64InstrInfo.h:149

@ MULADDv4i32_OP2

Definition AArch64InstrInfo.h:67

@ FMULADDS_OP1

Definition AArch64InstrInfo.h:105

@ MULADDv8i8_OP1

Definition AArch64InstrInfo.h:56

@ FMULADDD_OP1

Definition AArch64InstrInfo.h:109

@ MULSUBX_OP2

Definition AArch64InstrInfo.h:52

@ MULADDv2i32_OP2

Definition AArch64InstrInfo.h:65

@ MULADDv16i8_OP2

Definition AArch64InstrInfo.h:59

@ MULADDv8i8_OP2

Definition AArch64InstrInfo.h:57

@ FMULSUBH_OP1

Definition AArch64InstrInfo.h:103

@ FMLSv4i16_indexed_OP1

Definition AArch64InstrInfo.h:150

@ MULADDv16i8_OP1

Definition AArch64InstrInfo.h:58

@ FMLAv2i64_indexed_OP1

Definition AArch64InstrInfo.h:134

@ FMLAv1i32_indexed_OP2

Definition AArch64InstrInfo.h:117

@ FMLAv4f16_OP2

Definition AArch64InstrInfo.h:121

@ FMLSv2i64_indexed_OP2

Definition AArch64InstrInfo.h:157

@ MULADDv2i32_OP1

Definition AArch64InstrInfo.h:64

@ MULADDv4i32_OP1

Definition AArch64InstrInfo.h:66

@ FMLSv4f16_OP1

Definition AArch64InstrInfo.h:142

@ FMLSv8f16_OP2

Definition AArch64InstrInfo.h:145

@ FMLSv4f32_OP2

Definition AArch64InstrInfo.h:159

@ MULADDv2i32_indexed_OP1

Definition AArch64InstrInfo.h:86

@ FMULADDD_OP2

Definition AArch64InstrInfo.h:110

@ MULSUBv16i8_OP2

Definition AArch64InstrInfo.h:72

@ MULADDX_OP2

Definition AArch64InstrInfo.h:50

@ FMLSv4f32_OP1

Definition AArch64InstrInfo.h:158

@ MULADDv4i32_indexed_OP1

Definition AArch64InstrInfo.h:88

@ MULADDv2i32_indexed_OP2

Definition AArch64InstrInfo.h:87

@ FMLAv4i16_indexed_OP2

Definition AArch64InstrInfo.h:129

@ MULSUBv8i16_OP1

Definition AArch64InstrInfo.h:75

@ FMLAv8f16_OP2

Definition AArch64InstrInfo.h:123

@ FMULv2i32_indexed_OP2

Definition AArch64InstrInfo.h:164

@ FMLSv2f64_OP1

Definition AArch64InstrInfo.h:148

@ GATHER_LANE_i8

Definition AArch64InstrInfo.h:178

@ FMLSv2i32_indexed_OP2

Definition AArch64InstrInfo.h:155

@ FMULSUBS_OP1

Definition AArch64InstrInfo.h:107

@ FMLSv4i32_indexed_OP1

Definition AArch64InstrInfo.h:160

@ FMULv2i64_indexed_OP1

Definition AArch64InstrInfo.h:165

@ MULSUBv4i16_OP2

Definition AArch64InstrInfo.h:74

@ FMLSv4i16_indexed_OP2

Definition AArch64InstrInfo.h:151

@ FMLAv2i32_indexed_OP1

Definition AArch64InstrInfo.h:132

@ GATHER_LANE_i32

Definition AArch64InstrInfo.h:176

@ FMLSv2i32_indexed_OP1

Definition AArch64InstrInfo.h:154

@ FNMULSUBD_OP1

Definition AArch64InstrInfo.h:115

@ FMLAv8i16_indexed_OP1

Definition AArch64InstrInfo.h:130

@ MULSUBv4i16_indexed_OP1

Definition AArch64InstrInfo.h:91

@ MULADDW_OP2

Definition AArch64InstrInfo.h:44

@ FMULADDH_OP2

Definition AArch64InstrInfo.h:102

@ FMULADDS_OP2

Definition AArch64InstrInfo.h:106

@ FMLSv4i32_indexed_OP2

Definition AArch64InstrInfo.h:161

@ MULADDv4i32_indexed_OP2

Definition AArch64InstrInfo.h:89

@ MULSUBv4i32_OP2

Definition AArch64InstrInfo.h:80

@ MULSUBv8i16_indexed_OP1

Definition AArch64InstrInfo.h:93

@ MULADDv8i16_OP2

Definition AArch64InstrInfo.h:63

@ MULSUBv2i32_indexed_OP2

Definition AArch64InstrInfo.h:96

@ FMLSv8f16_OP1

Definition AArch64InstrInfo.h:144

@ MULADDW_OP1

Definition AArch64InstrInfo.h:43

@ FMULv4i32_indexed_OP2

Definition AArch64InstrInfo.h:170

@ FMLSv2i64_indexed_OP1

Definition AArch64InstrInfo.h:156

@ FMLAv2f32_OP2

Definition AArch64InstrInfo.h:124

@ FMLAv2f32_OP1

Definition AArch64InstrInfo.h:125

@ SUBADD_OP2

Definition AArch64InstrInfo.h:40

@ MULADDv4i16_OP1

Definition AArch64InstrInfo.h:60

@ FMLAv4i32_indexed_OP2

Definition AArch64InstrInfo.h:139

@ MULADDv8i16_indexed_OP1

Definition AArch64InstrInfo.h:84

@ FMLAv4f16_OP1

Definition AArch64InstrInfo.h:120

@ FMULv4i32_indexed_OP1

Definition AArch64InstrInfo.h:169

@ FMLAv4i16_indexed_OP1

Definition AArch64InstrInfo.h:128

@ FMULv8i16_indexed_OP1

Definition AArch64InstrInfo.h:171

@ MULSUBv8i8_OP1

Definition AArch64InstrInfo.h:69

@ MULSUBW_OP2

Definition AArch64InstrInfo.h:46

@ MULADDv8i16_OP1

Definition AArch64InstrInfo.h:62

@ MULSUBv4i32_indexed_OP1

Definition AArch64InstrInfo.h:97

@ MULSUBv4i32_OP1

Definition AArch64InstrInfo.h:79

@ FMLSv8i16_indexed_OP2

Definition AArch64InstrInfo.h:153

@ FMLAv4f32_OP2

Definition AArch64InstrInfo.h:137

@ MULADDv8i16_indexed_OP2

Definition AArch64InstrInfo.h:85

@ MULSUBWI_OP1

Definition AArch64InstrInfo.h:48

@ FMLAv4f32_OP1

Definition AArch64InstrInfo.h:136

@ MULSUBX_OP1

Definition AArch64InstrInfo.h:51

@ MULSUBv2i32_OP2

Definition AArch64InstrInfo.h:78

@ FMLSv1i64_indexed_OP2

Definition AArch64InstrInfo.h:141

@ MULADDv4i16_indexed_OP1

Definition AArch64InstrInfo.h:82

@ MULSUBv8i8_OP2

Definition AArch64InstrInfo.h:70

void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)

emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.

CombinerObjective

The combiner's goal may differ based on which pattern it is attempting to optimize.

std::optional< UsedNZCV > examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > *CCUseInstrs=nullptr)

CodeGenOptLevel

Code generation optimization level.

MCCFIInstruction createCFAOffset(const TargetRegisterInfo &MRI, unsigned Reg, const StackOffset &OffsetFromDefCFA, std::optional< int64_t > IncomingVGOffsetFromDefCFA)

ArrayRef(const T &OneElt) -> ArrayRef< T >

static bool isUncondBranchOpcode(int Opc)

Definition AArch64InstrInfo.h:708

static unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero)

Return PAC opcode to be used for a ptrauth sign using the given key, or its PAC*Z variant that doesn'...

Definition AArch64InstrInfo.h:798

bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, StackOffset &Offset, const AArch64InstrInfo *TII)

rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.

static const MachineMemOperand::Flags MOSuppressPair

Definition AArch64InstrInfo.h:29

bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)

Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...

static const MachineMemOperand::Flags MOStridedAccess

Definition AArch64InstrInfo.h:31

static unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero)

Return AUT opcode to be used for a ptrauth auth using the given key, or its AUT*Z variant that doesn'...

Definition AArch64InstrInfo.h:785

Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.

UsedNZCV & operator|=(const UsedNZCV &UsedFlags)

Definition AArch64InstrInfo.h:629

bool V

Definition AArch64InstrInfo.h:625

bool C

Definition AArch64InstrInfo.h:624

bool N

Definition AArch64InstrInfo.h:622

bool Z

Definition AArch64InstrInfo.h:623

An individual sequence of instructions to be replaced with a call to an outlined function.

The information necessary to create an outlined function for some class of candidate.