AArch64MCCodeEmitter.cpp Source File (original) (raw)

28#include

29#include

31using namespace llvm;

33#define DEBUG_TYPE "mccodeemitter"

35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");

36 STATISTIC(MCNumFixups, "Number of MC fixups created.");

38namespace {

40class AArch64MCCodeEmitter : public MCCodeEmitter {

43public:

45 AArch64MCCodeEmitter(const AArch64MCCodeEmitter &) = delete;

46 void operator=(const AArch64MCCodeEmitter &) = delete;

47 ~AArch64MCCodeEmitter() override = default;

51 uint64_t getBinaryCodeForInstr(const MCInst &MI,

52 SmallVectorImpl &Fixups,

53 const MCSubtargetInfo &STI) const;

57 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,

58 SmallVectorImpl &Fixups,

59 const MCSubtargetInfo &STI) const;

64 template <uint32_t FixupKind>

65 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,

66 SmallVectorImpl &Fixups,

67 const MCSubtargetInfo &STI) const;

71 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,

72 SmallVectorImpl &Fixups,

73 const MCSubtargetInfo &STI) const;

77 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,

78 SmallVectorImpl &Fixups,

79 const MCSubtargetInfo &STI) const;

83 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,

84 SmallVectorImpl &Fixups,

85 const MCSubtargetInfo &STI) const;

89 uint32_t getCondCompBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,

90 SmallVectorImpl &Fixups,

91 const MCSubtargetInfo &STI) const;

95 uint32_t getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,

96 SmallVectorImpl &Fixups,

97 const MCSubtargetInfo &STI) const;

100

101 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,

102 SmallVectorImpl &Fixups,

103 const MCSubtargetInfo &STI) const;

104

105

106

107

108 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,

109 SmallVectorImpl &Fixups,

110 const MCSubtargetInfo &STI) const;

111

112

113

114 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,

115 SmallVectorImpl &Fixups,

116 const MCSubtargetInfo &STI) const;

117

118

119

121 SmallVectorImpl &Fixups,

122 const MCSubtargetInfo &STI) const;

123

124

125

126 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,

127 SmallVectorImpl &Fixups,

128 const MCSubtargetInfo &STI) const;

129

130

131 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,

132 SmallVectorImpl &Fixups,

133 const MCSubtargetInfo &STI) const;

134

135

136

137 uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,

138 SmallVectorImpl &Fixups,

139 const MCSubtargetInfo &STI) const;

140

141

142

143 uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,

144 SmallVectorImpl &Fixups,

145 const MCSubtargetInfo &STI) const;

146

147 uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,

148 SmallVectorImpl &Fixups,

149 const MCSubtargetInfo &STI) const;

150 uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,

151 SmallVectorImpl &Fixups,

152 const MCSubtargetInfo &STI) const;

153 uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,

154 SmallVectorImpl &Fixups,

155 const MCSubtargetInfo &STI) const;

156 uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,

157 SmallVectorImpl &Fixups,

158 const MCSubtargetInfo &STI) const;

159 uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,

160 SmallVectorImpl &Fixups,

161 const MCSubtargetInfo &STI) const;

162 uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,

163 SmallVectorImpl &Fixups,

164 const MCSubtargetInfo &STI) const;

165 uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,

166 SmallVectorImpl &Fixups,

167 const MCSubtargetInfo &STI) const;

168 uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,

169 SmallVectorImpl &Fixups,

170 const MCSubtargetInfo &STI) const;

171

172 uint32_t getImm8OptLsl(const MCInst &MI, unsigned OpIdx,

173 SmallVectorImpl &Fixups,

174 const MCSubtargetInfo &STI) const;

175 uint32_t getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,

176 SmallVectorImpl &Fixups,

177 const MCSubtargetInfo &STI) const;

178

179 unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,

180 const MCSubtargetInfo &STI) const;

181

182 void encodeInstruction(const MCInst &MI, SmallVectorImpl &CB,

183 SmallVectorImpl &Fixups,

184 const MCSubtargetInfo &STI) const override;

185

186 unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,

187 const MCSubtargetInfo &STI) const;

188

189 template<int hasRs, int hasRt2> unsigned

190 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,

191 const MCSubtargetInfo &STI) const;

192

193 unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,

194 const MCSubtargetInfo &STI) const;

195

196 template <unsigned Multiple, unsigned Min, unsigned Max>

197 uint32_t EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,

198 SmallVectorImpl &Fixups,

199 const MCSubtargetInfo &STI) const;

200 uint32_t EncodeZK(const MCInst &MI, unsigned OpIdx,

201 SmallVectorImpl &Fixups,

202 const MCSubtargetInfo &STI) const;

203 uint32_t EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,

204 SmallVectorImpl &Fixups,

205 const MCSubtargetInfo &STI) const;

206

207 uint32_t EncodeZPR2StridedRegisterClass(const MCInst &MI, unsigned OpIdx,

208 SmallVectorImpl &Fixups,

209 const MCSubtargetInfo &STI) const;

210 uint32_t EncodeZPR4StridedRegisterClass(const MCInst &MI, unsigned OpIdx,

211 SmallVectorImpl &Fixups,

212 const MCSubtargetInfo &STI) const;

213

214 uint32_t EncodeMatrixTileListRegisterClass(const MCInst &MI, unsigned OpIdx,

215 SmallVectorImpl &Fixups,

216 const MCSubtargetInfo &STI) const;

217 template

218 uint32_t encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,

219 SmallVectorImpl &Fixups,

220 const MCSubtargetInfo &STI) const;

221};

222

223}

224

229

230

231

232unsigned

233AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,

238

239 assert(MO.isImm() && "did not expect relocated expression");

240 return static_cast<unsigned>(MO.getImm());

241}

242

243template uint32_t

244AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,

245 SmallVectorImpl &Fixups,

246 const MCSubtargetInfo &STI) const {

247 const MCOperand &MO = MI.getOperand(OpIdx);

248 uint32_t ImmVal = 0;

249

251 ImmVal = static_cast<uint32_t>(MO.getImm());

252 else {

253 assert(MO.isExpr() && "unable to encode load/store imm operand");

256 ++MCNumFixups;

257 }

258

259 return ImmVal;

260}

261

262

263

264uint32_t

265AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,

266 SmallVectorImpl &Fixups,

267 const MCSubtargetInfo &STI) const {

268 const MCOperand &MO = MI.getOperand(OpIdx);

269

270

273 assert(MO.isExpr() && "Unexpected target type!");

274 const MCExpr *Expr = MO.getExpr();

275

276 unsigned Kind = MI.getOpcode() == AArch64::ADR

279 addFixup(Fixups, 0, Expr, Kind, true);

280 MCNumFixups += 1;

281 return 0;

282}

283

284

285

286

287uint32_t

288AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,

289 SmallVectorImpl &Fixups,

290 const MCSubtargetInfo &STI) const {

291

292 const MCOperand &MO = MI.getOperand(OpIdx);

293 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);

295 "unexpected shift type for add/sub immediate");

297 assert((ShiftVal == 0 || ShiftVal == 12) &&

298 "unexpected shift value for add/sub immediate");

300 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal));

301 assert(MO.isExpr() && "Unable to encode MCOperand!");

302 const MCExpr *Expr = MO.getExpr();

303

304

306 addFixup(Fixups, 0, Expr, Kind);

307

308 ++MCNumFixups;

309

310

311

316 ShiftVal = 12;

317 }

318 return ShiftVal == 0 ? 0 : (1 << ShiftVal);

319}

320

321

322

323uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(

324 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,

325 const MCSubtargetInfo &STI) const {

326 const MCOperand &MO = MI.getOperand(OpIdx);

327

328

331 assert(MO.isExpr() && "Unexpected target type!");

332

334 true);

335 ++MCNumFixups;

336 return 0;

337}

338

339

340

341uint32_t AArch64MCCodeEmitter::getCondCompBranchTargetOpValue(

342 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,

343 const MCSubtargetInfo &STI) const {

344 const MCOperand &MO = MI.getOperand(OpIdx);

345

346

349 assert(MO.isExpr() && "Unexpected target type!");

350

353 ++MCNumFixups;

354 return 0;

355}

356

357

358

359uint32_t

360AArch64MCCodeEmitter::getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,

361 SmallVectorImpl &Fixups,

362 const MCSubtargetInfo &STI) const {

363 const MCOperand &MO = MI.getOperand(OpIdx);

364

365

366

368 return -(MO.getImm());

369 assert(MO.isExpr() && "Unexpected target type!");

370

372 true);

373 ++MCNumFixups;

374 return 0;

375}

376

377

378

379uint32_t

380AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,

381 SmallVectorImpl &Fixups,

382 const MCSubtargetInfo &STI) const {

383 const MCOperand &MO = MI.getOperand(OpIdx);

384

385

388 assert(MO.isExpr() && "Unexpected target type!");

389

391 true);

392 ++MCNumFixups;

393 return 0;

394}

395

396uint32_t

397AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,

398 SmallVectorImpl &Fixups,

399 const MCSubtargetInfo &STI) const {

400 unsigned SignExtend = MI.getOperand(OpIdx).getImm();

401 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm();

402 return (SignExtend << 1) | DoShift;

403}

404

405uint32_t

406AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,

407 SmallVectorImpl &Fixups,

408 const MCSubtargetInfo &STI) const {

409 const MCOperand &MO = MI.getOperand(OpIdx);

410

413 assert(MO.isExpr() && "Unexpected movz/movk immediate");

414

417

418 ++MCNumFixups;

419

420 return 0;

421}

422

423

424

425uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(

426 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,

427 const MCSubtargetInfo &STI) const {

428 const MCOperand &MO = MI.getOperand(OpIdx);

429

430

433 assert(MO.isExpr() && "Unexpected ADR target type!");

434

436 true);

437 ++MCNumFixups;

438 return 0;

439}

440

441

442

443uint32_t

444AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,

445 SmallVectorImpl &Fixups,

446 const MCSubtargetInfo &STI) const {

447 const MCOperand &MO = MI.getOperand(OpIdx);

448

449

452 assert(MO.isExpr() && "Unexpected ADR target type!");

453

454 unsigned Kind = MI.getOpcode() == AArch64::BL

458

459 ++MCNumFixups;

460

461

462 return 0;

463}

464

465

466

467

468

469

470

471uint32_t

472AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,

473 SmallVectorImpl &Fixups,

474 const MCSubtargetInfo &STI) const {

475 const MCOperand &MO = MI.getOperand(OpIdx);

476 assert(MO.isImm() && "Expected an immediate value for the shift amount!");

477

478 switch (MO.getImm()) {

479 default:

480 break;

481 case 0:

482 return 0;

483 case 8:

484 return 1;

485 case 16:

486 return 2;

487 case 24:

488 return 3;

489 }

490

492}

493

494

495

496uint32_t AArch64MCCodeEmitter::getFixedPointScaleOpValue(

497 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,

498 const MCSubtargetInfo &STI) const {

499 const MCOperand &MO = MI.getOperand(OpIdx);

500 assert(MO.isImm() && "Expected an immediate value for the scale amount!");

501 return 64 - MO.getImm();

502}

503

504uint32_t

505AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,

506 SmallVectorImpl &Fixups,

507 const MCSubtargetInfo &STI) const {

508 const MCOperand &MO = MI.getOperand(OpIdx);

509 assert(MO.isImm() && "Expected an immediate value for the scale amount!");

510 return 64 - MO.getImm();

511}

512

513uint32_t

514AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,

515 SmallVectorImpl &Fixups,

516 const MCSubtargetInfo &STI) const {

517 const MCOperand &MO = MI.getOperand(OpIdx);

518 assert(MO.isImm() && "Expected an immediate value for the scale amount!");

519 return 32 - MO.getImm();

520}

521

522uint32_t

523AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,

524 SmallVectorImpl &Fixups,

525 const MCSubtargetInfo &STI) const {

526 const MCOperand &MO = MI.getOperand(OpIdx);

527 assert(MO.isImm() && "Expected an immediate value for the scale amount!");

528 return 16 - MO.getImm();

529}

530

531uint32_t

532AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,

533 SmallVectorImpl &Fixups,

534 const MCSubtargetInfo &STI) const {

535 const MCOperand &MO = MI.getOperand(OpIdx);

536 assert(MO.isImm() && "Expected an immediate value for the scale amount!");

537 return 8 - MO.getImm();

538}

539

540uint32_t

541AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,

542 SmallVectorImpl &Fixups,

543 const MCSubtargetInfo &STI) const {

544 const MCOperand &MO = MI.getOperand(OpIdx);

545 assert(MO.isImm() && "Expected an immediate value for the scale amount!");

546 return MO.getImm() - 64;

547}

548

549uint32_t

550AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,

551 SmallVectorImpl &Fixups,

552 const MCSubtargetInfo &STI) const {

553 const MCOperand &MO = MI.getOperand(OpIdx);

554 assert(MO.isImm() && "Expected an immediate value for the scale amount!");

555 return MO.getImm() - 32;

556}

557

558uint32_t

559AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,

560 SmallVectorImpl &Fixups,

561 const MCSubtargetInfo &STI) const {

562 const MCOperand &MO = MI.getOperand(OpIdx);

563 assert(MO.isImm() && "Expected an immediate value for the scale amount!");

564 return MO.getImm() - 16;

565}

566

567uint32_t

568AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,

569 SmallVectorImpl &Fixups,

570 const MCSubtargetInfo &STI) const {

571 const MCOperand &MO = MI.getOperand(OpIdx);

572 assert(MO.isImm() && "Expected an immediate value for the scale amount!");

573 return MO.getImm() - 8;

574}

575

576template <unsigned Multiple, unsigned Min, unsigned Max>

577uint32_t

578AArch64MCCodeEmitter::EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,

579 SmallVectorImpl &Fixups,

580 const MCSubtargetInfo &STI) const {

582 auto RegOpnd = MI.getOperand(OpIdx).getReg();

584 assert(RegVal >= Min && RegVal <= Max && (RegVal & (Multiple - 1)) == 0);

585 return (RegVal - Min) / Multiple;

586}

587

588

589

590

591uint32_t AArch64MCCodeEmitter::EncodeZK(const MCInst &MI, unsigned OpIdx,

592 SmallVectorImpl &Fixups,

593 const MCSubtargetInfo &STI) const {

594 auto RegOpnd = MI.getOperand(OpIdx).getReg();

596

597

598 if (RegOpnd > AArch64::Z27)

599 return (RegVal - 24);

600

601 assert((RegOpnd > AArch64::Z19 && RegOpnd < AArch64::Z24) &&

602 "Expected ZK in Z20..Z23 or Z28..Z31");

603

604 return (RegVal - 20);

605}

606

607uint32_t

608AArch64MCCodeEmitter::EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,

609 SmallVectorImpl &Fixups,

610 const MCSubtargetInfo &STI) const {

611 auto RegOpnd = MI.getOperand(OpIdx).getReg();

612 return RegOpnd - AArch64::PN8;

613}

614

615uint32_t AArch64MCCodeEmitter::EncodeZPR2StridedRegisterClass(

616 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,

617 const MCSubtargetInfo &STI) const {

618 auto RegOpnd = MI.getOperand(OpIdx).getReg();

620 unsigned T = (RegVal & 0x10) >> 1;

621 unsigned Zt = RegVal & 0x7;

622 return T | Zt;

623}

624

625uint32_t AArch64MCCodeEmitter::EncodeZPR4StridedRegisterClass(

626 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,

627 const MCSubtargetInfo &STI) const {

628 auto RegOpnd = MI.getOperand(OpIdx).getReg();

630 unsigned T = (RegVal & 0x10) >> 2;

631 unsigned Zt = RegVal & 0x3;

632 return T | Zt;

633}

634

635uint32_t AArch64MCCodeEmitter::EncodeMatrixTileListRegisterClass(

636 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,

637 const MCSubtargetInfo &STI) const {

638 unsigned RegMask = MI.getOperand(OpIdx).getImm();

639 assert(RegMask <= 0xFF && "Invalid register mask!");

640 return RegMask;

641}

642

643template

644uint32_t

645AArch64MCCodeEmitter::encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,

646 SmallVectorImpl &Fixups,

647 const MCSubtargetInfo &STI) const {

648 auto RegOpnd = MI.getOperand(OpIdx).getReg();

649 return RegOpnd - BaseReg;

650}

651

652uint32_t

653AArch64MCCodeEmitter::getImm8OptLsl(const MCInst &MI, unsigned OpIdx,

654 SmallVectorImpl &Fixups,

655 const MCSubtargetInfo &STI) const {

656

657 auto ShiftOpnd = MI.getOperand(OpIdx + 1).getImm();

659 "Unexpected shift type for imm8_opt_lsl immediate.");

660

662 assert((ShiftVal == 0 || ShiftVal == 8) &&

663 "Unexpected shift value for imm8_opt_lsl immediate.");

664

665

666 auto Immediate = MI.getOperand(OpIdx).getImm();

667 return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal));

668}

669

670uint32_t

671AArch64MCCodeEmitter::getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,

672 SmallVectorImpl &Fixups,

673 const MCSubtargetInfo &STI) const {

674 const MCOperand &MO = MI.getOperand(OpIdx);

675 assert(MO.isImm() && "Expected an immediate value!");

676

677 return MO.getImm() - 1;

678}

679

680

681

682uint32_t AArch64MCCodeEmitter::getMoveVecShifterOpValue(

683 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,

684 const MCSubtargetInfo &STI) const {

685 const MCOperand &MO = MI.getOperand(OpIdx);

687 "Expected an immediate value for the move shift amount!");

689 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!");

690 return ShiftVal == 8 ? 0 : 1;

691}

692

693unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,

694 const MCSubtargetInfo &STI) const {

695

696

697

698

699 MCOperand UImm16MO = MI.getOperand(1);

700

701

702 if (UImm16MO.isImm())

703 return EncodedValue;

704

705 const MCExpr *E = UImm16MO.getExpr();

707 switch (A64E->getSpecifier()) {

715 return EncodedValue & ~(1u << 30);

716 default:

717

718 return EncodedValue;

719 }

720 }

721

722 return EncodedValue;

723}

724

725void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI,

726 SmallVectorImpl &CB,

727

728 SmallVectorImpl &Fixups,

729 const MCSubtargetInfo &STI) const {

730 if (MI.getOpcode() == AArch64::TLSDESCCALL) {

731

732

733

735 ? ELF::R_AARCH64_P32_TLSDESC_CALL

736 : ELF::R_AARCH64_TLSDESC_CALL;

737 addFixup(Fixups, 0, MI.getOperand(0).getExpr(), Reloc);

738 return;

739 }

740

741 if (MI.getOpcode() == AArch64::SPACE) {

742

743 return;

744 }

745

746 uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);

748 ++MCNumEmitted;

749}

750

751unsigned

752AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,

753 unsigned EncodedValue,

754 const MCSubtargetInfo &STI) const {

755

756

757 EncodedValue |= 0x1f << 10;

758 return EncodedValue;

759}

760

761template<int hasRs, int hasRt2> unsigned

762AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,

763 unsigned EncodedValue,

764 const MCSubtargetInfo &STI) const {

765 if (!hasRs) EncodedValue |= 0x001F0000;

766 if (!hasRt2) EncodedValue |= 0x00007C00;

767

768 return EncodedValue;

769}

770

771unsigned AArch64MCCodeEmitter::fixOneOperandFPComparison(

772 const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const {

773

774

775 EncodedValue &= ~(0x1f << 16);

776 return EncodedValue;

777}

778

779#include "AArch64GenMCCodeEmitter.inc"

780

783 return new AArch64MCCodeEmitter(MCII, Ctx);

784}

static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind, bool PCRel=false)

Definition AArch64MCCodeEmitter.cpp:225

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)

getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

MachineInstr unsigned OpIdx

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

MCCodeEmitter - Generic instruction encoding interface.

Context object for machine code objects.

const MCRegisterInfo * getRegisterInfo() const

Base class for the full range of assembler expressions which are needed for parsing.

static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)

Consider bit fields if we need more flags.

Instances of this class represent a single low-level machine instruction.

Interface to description of machine instruction set.

Instances of this class represent operands of the MCInst class.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

uint16_t getEncodingValue(MCRegister Reg) const

Returns the encoding for Reg.

Generic base class for all target subtargets.

const Triple & getTargetTriple() const

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

EnvironmentType getEnvironment() const

Get the parsed environment type of this triple.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

static unsigned getShiftValue(unsigned Imm)

getShiftValue - Extract the shift value.

static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)

getShiftType - Extract the shift type.

@ fixup_aarch64_pcrel_branch9

@ fixup_aarch64_pcrel_branch16

@ fixup_aarch64_pcrel_call26

@ fixup_aarch64_pcrel_branch26

@ fixup_aarch64_pcrel_branch19

@ fixup_aarch64_ldr_pcrel_imm19

@ fixup_aarch64_pcrel_adr_imm21

@ fixup_aarch64_pcrel_branch14

@ fixup_aarch64_pcrel_adrp_imm21

@ fixup_aarch64_add_imm12

BaseReg

Stack frame base register. Bit 0 of FREInfo.Info.

void write(void *memory, value_type value, endianness endian)

Write a value to memory with a particular endianness.

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

uint16_t MCFixupKind

Extensible enumeration to represent the type of a fixup.

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

static Lanai::Fixups FixupKind(const MCExpr *Expr)

MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

Definition AArch64MCCodeEmitter.cpp:781