AArch64MCTargetDesc.cpp Source File (original) (raw)

50 InitAArch64MCInstrInfo(X);

51 return X;

52}

58 if (CPU.empty()) {

59 CPU = "generic";

60 if (FS.empty())

61 FS = "+v8a";

63 if (TT.isArm64e())

64 CPU = "apple-a12";

65 }

67 return createAArch64MCSubtargetInfoImpl(TT, CPU, CPU, FS);

68}

72 static const struct {

75 } RegMap[] = {

76 {codeview::RegisterId::ARM64_W0, AArch64::W0},

77 {codeview::RegisterId::ARM64_W1, AArch64::W1},

78 {codeview::RegisterId::ARM64_W2, AArch64::W2},

79 {codeview::RegisterId::ARM64_W3, AArch64::W3},

80 {codeview::RegisterId::ARM64_W4, AArch64::W4},

81 {codeview::RegisterId::ARM64_W5, AArch64::W5},

82 {codeview::RegisterId::ARM64_W6, AArch64::W6},

83 {codeview::RegisterId::ARM64_W7, AArch64::W7},

84 {codeview::RegisterId::ARM64_W8, AArch64::W8},

85 {codeview::RegisterId::ARM64_W9, AArch64::W9},

86 {codeview::RegisterId::ARM64_W10, AArch64::W10},

87 {codeview::RegisterId::ARM64_W11, AArch64::W11},

88 {codeview::RegisterId::ARM64_W12, AArch64::W12},

89 {codeview::RegisterId::ARM64_W13, AArch64::W13},

90 {codeview::RegisterId::ARM64_W14, AArch64::W14},

91 {codeview::RegisterId::ARM64_W15, AArch64::W15},

92 {codeview::RegisterId::ARM64_W16, AArch64::W16},

93 {codeview::RegisterId::ARM64_W17, AArch64::W17},

94 {codeview::RegisterId::ARM64_W18, AArch64::W18},

95 {codeview::RegisterId::ARM64_W19, AArch64::W19},

96 {codeview::RegisterId::ARM64_W20, AArch64::W20},

97 {codeview::RegisterId::ARM64_W21, AArch64::W21},

98 {codeview::RegisterId::ARM64_W22, AArch64::W22},

99 {codeview::RegisterId::ARM64_W23, AArch64::W23},

100 {codeview::RegisterId::ARM64_W24, AArch64::W24},

101 {codeview::RegisterId::ARM64_W25, AArch64::W25},

102 {codeview::RegisterId::ARM64_W26, AArch64::W26},

103 {codeview::RegisterId::ARM64_W27, AArch64::W27},

104 {codeview::RegisterId::ARM64_W28, AArch64::W28},

105 {codeview::RegisterId::ARM64_W29, AArch64::W29},

106 {codeview::RegisterId::ARM64_W30, AArch64::W30},

107 {codeview::RegisterId::ARM64_WZR, AArch64::WZR},

108 {codeview::RegisterId::ARM64_X0, AArch64::X0},

109 {codeview::RegisterId::ARM64_X1, AArch64::X1},

110 {codeview::RegisterId::ARM64_X2, AArch64::X2},

111 {codeview::RegisterId::ARM64_X3, AArch64::X3},

112 {codeview::RegisterId::ARM64_X4, AArch64::X4},

113 {codeview::RegisterId::ARM64_X5, AArch64::X5},

114 {codeview::RegisterId::ARM64_X6, AArch64::X6},

115 {codeview::RegisterId::ARM64_X7, AArch64::X7},

116 {codeview::RegisterId::ARM64_X8, AArch64::X8},

117 {codeview::RegisterId::ARM64_X9, AArch64::X9},

118 {codeview::RegisterId::ARM64_X10, AArch64::X10},

119 {codeview::RegisterId::ARM64_X11, AArch64::X11},

120 {codeview::RegisterId::ARM64_X12, AArch64::X12},

121 {codeview::RegisterId::ARM64_X13, AArch64::X13},

122 {codeview::RegisterId::ARM64_X14, AArch64::X14},

123 {codeview::RegisterId::ARM64_X15, AArch64::X15},

124 {codeview::RegisterId::ARM64_X16, AArch64::X16},

125 {codeview::RegisterId::ARM64_X17, AArch64::X17},

126 {codeview::RegisterId::ARM64_X18, AArch64::X18},

127 {codeview::RegisterId::ARM64_X19, AArch64::X19},

128 {codeview::RegisterId::ARM64_X20, AArch64::X20},

129 {codeview::RegisterId::ARM64_X21, AArch64::X21},

130 {codeview::RegisterId::ARM64_X22, AArch64::X22},

131 {codeview::RegisterId::ARM64_X23, AArch64::X23},

132 {codeview::RegisterId::ARM64_X24, AArch64::X24},

133 {codeview::RegisterId::ARM64_X25, AArch64::X25},

134 {codeview::RegisterId::ARM64_X26, AArch64::X26},

135 {codeview::RegisterId::ARM64_X27, AArch64::X27},

136 {codeview::RegisterId::ARM64_X28, AArch64::X28},

137 {codeview::RegisterId::ARM64_FP, AArch64::FP},

138 {codeview::RegisterId::ARM64_LR, AArch64::LR},

139 {codeview::RegisterId::ARM64_SP, AArch64::SP},

140 {codeview::RegisterId::ARM64_ZR, AArch64::XZR},

141 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},

142 {codeview::RegisterId::ARM64_S0, AArch64::S0},

143 {codeview::RegisterId::ARM64_S1, AArch64::S1},

144 {codeview::RegisterId::ARM64_S2, AArch64::S2},

145 {codeview::RegisterId::ARM64_S3, AArch64::S3},

146 {codeview::RegisterId::ARM64_S4, AArch64::S4},

147 {codeview::RegisterId::ARM64_S5, AArch64::S5},

148 {codeview::RegisterId::ARM64_S6, AArch64::S6},

149 {codeview::RegisterId::ARM64_S7, AArch64::S7},

150 {codeview::RegisterId::ARM64_S8, AArch64::S8},

151 {codeview::RegisterId::ARM64_S9, AArch64::S9},

152 {codeview::RegisterId::ARM64_S10, AArch64::S10},

153 {codeview::RegisterId::ARM64_S11, AArch64::S11},

154 {codeview::RegisterId::ARM64_S12, AArch64::S12},

155 {codeview::RegisterId::ARM64_S13, AArch64::S13},

156 {codeview::RegisterId::ARM64_S14, AArch64::S14},

157 {codeview::RegisterId::ARM64_S15, AArch64::S15},

158 {codeview::RegisterId::ARM64_S16, AArch64::S16},

159 {codeview::RegisterId::ARM64_S17, AArch64::S17},

160 {codeview::RegisterId::ARM64_S18, AArch64::S18},

161 {codeview::RegisterId::ARM64_S19, AArch64::S19},

162 {codeview::RegisterId::ARM64_S20, AArch64::S20},

163 {codeview::RegisterId::ARM64_S21, AArch64::S21},

164 {codeview::RegisterId::ARM64_S22, AArch64::S22},

165 {codeview::RegisterId::ARM64_S23, AArch64::S23},

166 {codeview::RegisterId::ARM64_S24, AArch64::S24},

167 {codeview::RegisterId::ARM64_S25, AArch64::S25},

168 {codeview::RegisterId::ARM64_S26, AArch64::S26},

169 {codeview::RegisterId::ARM64_S27, AArch64::S27},

170 {codeview::RegisterId::ARM64_S28, AArch64::S28},

171 {codeview::RegisterId::ARM64_S29, AArch64::S29},

172 {codeview::RegisterId::ARM64_S30, AArch64::S30},

173 {codeview::RegisterId::ARM64_S31, AArch64::S31},

174 {codeview::RegisterId::ARM64_D0, AArch64::D0},

175 {codeview::RegisterId::ARM64_D1, AArch64::D1},

176 {codeview::RegisterId::ARM64_D2, AArch64::D2},

177 {codeview::RegisterId::ARM64_D3, AArch64::D3},

178 {codeview::RegisterId::ARM64_D4, AArch64::D4},

179 {codeview::RegisterId::ARM64_D5, AArch64::D5},

180 {codeview::RegisterId::ARM64_D6, AArch64::D6},

181 {codeview::RegisterId::ARM64_D7, AArch64::D7},

182 {codeview::RegisterId::ARM64_D8, AArch64::D8},

183 {codeview::RegisterId::ARM64_D9, AArch64::D9},

184 {codeview::RegisterId::ARM64_D10, AArch64::D10},

185 {codeview::RegisterId::ARM64_D11, AArch64::D11},

186 {codeview::RegisterId::ARM64_D12, AArch64::D12},

187 {codeview::RegisterId::ARM64_D13, AArch64::D13},

188 {codeview::RegisterId::ARM64_D14, AArch64::D14},

189 {codeview::RegisterId::ARM64_D15, AArch64::D15},

190 {codeview::RegisterId::ARM64_D16, AArch64::D16},

191 {codeview::RegisterId::ARM64_D17, AArch64::D17},

192 {codeview::RegisterId::ARM64_D18, AArch64::D18},

193 {codeview::RegisterId::ARM64_D19, AArch64::D19},

194 {codeview::RegisterId::ARM64_D20, AArch64::D20},

195 {codeview::RegisterId::ARM64_D21, AArch64::D21},

196 {codeview::RegisterId::ARM64_D22, AArch64::D22},

197 {codeview::RegisterId::ARM64_D23, AArch64::D23},

198 {codeview::RegisterId::ARM64_D24, AArch64::D24},

199 {codeview::RegisterId::ARM64_D25, AArch64::D25},

200 {codeview::RegisterId::ARM64_D26, AArch64::D26},

201 {codeview::RegisterId::ARM64_D27, AArch64::D27},

202 {codeview::RegisterId::ARM64_D28, AArch64::D28},

203 {codeview::RegisterId::ARM64_D29, AArch64::D29},

204 {codeview::RegisterId::ARM64_D30, AArch64::D30},

205 {codeview::RegisterId::ARM64_D31, AArch64::D31},

206 {codeview::RegisterId::ARM64_Q0, AArch64::Q0},

207 {codeview::RegisterId::ARM64_Q1, AArch64::Q1},

208 {codeview::RegisterId::ARM64_Q2, AArch64::Q2},

209 {codeview::RegisterId::ARM64_Q3, AArch64::Q3},

210 {codeview::RegisterId::ARM64_Q4, AArch64::Q4},

211 {codeview::RegisterId::ARM64_Q5, AArch64::Q5},

212 {codeview::RegisterId::ARM64_Q6, AArch64::Q6},

213 {codeview::RegisterId::ARM64_Q7, AArch64::Q7},

214 {codeview::RegisterId::ARM64_Q8, AArch64::Q8},

215 {codeview::RegisterId::ARM64_Q9, AArch64::Q9},

216 {codeview::RegisterId::ARM64_Q10, AArch64::Q10},

217 {codeview::RegisterId::ARM64_Q11, AArch64::Q11},

218 {codeview::RegisterId::ARM64_Q12, AArch64::Q12},

219 {codeview::RegisterId::ARM64_Q13, AArch64::Q13},

220 {codeview::RegisterId::ARM64_Q14, AArch64::Q14},

221 {codeview::RegisterId::ARM64_Q15, AArch64::Q15},

222 {codeview::RegisterId::ARM64_Q16, AArch64::Q16},

223 {codeview::RegisterId::ARM64_Q17, AArch64::Q17},

224 {codeview::RegisterId::ARM64_Q18, AArch64::Q18},

225 {codeview::RegisterId::ARM64_Q19, AArch64::Q19},

226 {codeview::RegisterId::ARM64_Q20, AArch64::Q20},

227 {codeview::RegisterId::ARM64_Q21, AArch64::Q21},

228 {codeview::RegisterId::ARM64_Q22, AArch64::Q22},

229 {codeview::RegisterId::ARM64_Q23, AArch64::Q23},

230 {codeview::RegisterId::ARM64_Q24, AArch64::Q24},

231 {codeview::RegisterId::ARM64_Q25, AArch64::Q25},

232 {codeview::RegisterId::ARM64_Q26, AArch64::Q26},

233 {codeview::RegisterId::ARM64_Q27, AArch64::Q27},

234 {codeview::RegisterId::ARM64_Q28, AArch64::Q28},

235 {codeview::RegisterId::ARM64_Q29, AArch64::Q29},

236 {codeview::RegisterId::ARM64_Q30, AArch64::Q30},

237 {codeview::RegisterId::ARM64_Q31, AArch64::Q31},

238 {codeview::RegisterId::ARM64_B0, AArch64::B0},

239 {codeview::RegisterId::ARM64_B1, AArch64::B1},

240 {codeview::RegisterId::ARM64_B2, AArch64::B2},

241 {codeview::RegisterId::ARM64_B3, AArch64::B3},

242 {codeview::RegisterId::ARM64_B4, AArch64::B4},

243 {codeview::RegisterId::ARM64_B5, AArch64::B5},

244 {codeview::RegisterId::ARM64_B6, AArch64::B6},

245 {codeview::RegisterId::ARM64_B7, AArch64::B7},

246 {codeview::RegisterId::ARM64_B8, AArch64::B8},

247 {codeview::RegisterId::ARM64_B9, AArch64::B9},

248 {codeview::RegisterId::ARM64_B10, AArch64::B10},

249 {codeview::RegisterId::ARM64_B11, AArch64::B11},

250 {codeview::RegisterId::ARM64_B12, AArch64::B12},

251 {codeview::RegisterId::ARM64_B13, AArch64::B13},

252 {codeview::RegisterId::ARM64_B14, AArch64::B14},

253 {codeview::RegisterId::ARM64_B15, AArch64::B15},

254 {codeview::RegisterId::ARM64_B16, AArch64::B16},

255 {codeview::RegisterId::ARM64_B17, AArch64::B17},

256 {codeview::RegisterId::ARM64_B18, AArch64::B18},

257 {codeview::RegisterId::ARM64_B19, AArch64::B19},

258 {codeview::RegisterId::ARM64_B20, AArch64::B20},

259 {codeview::RegisterId::ARM64_B21, AArch64::B21},

260 {codeview::RegisterId::ARM64_B22, AArch64::B22},

261 {codeview::RegisterId::ARM64_B23, AArch64::B23},

262 {codeview::RegisterId::ARM64_B24, AArch64::B24},

263 {codeview::RegisterId::ARM64_B25, AArch64::B25},

264 {codeview::RegisterId::ARM64_B26, AArch64::B26},

265 {codeview::RegisterId::ARM64_B27, AArch64::B27},

266 {codeview::RegisterId::ARM64_B28, AArch64::B28},

267 {codeview::RegisterId::ARM64_B29, AArch64::B29},

268 {codeview::RegisterId::ARM64_B30, AArch64::B30},

269 {codeview::RegisterId::ARM64_B31, AArch64::B31},

270 {codeview::RegisterId::ARM64_H0, AArch64::H0},

271 {codeview::RegisterId::ARM64_H1, AArch64::H1},

272 {codeview::RegisterId::ARM64_H2, AArch64::H2},

273 {codeview::RegisterId::ARM64_H3, AArch64::H3},

274 {codeview::RegisterId::ARM64_H4, AArch64::H4},

275 {codeview::RegisterId::ARM64_H5, AArch64::H5},

276 {codeview::RegisterId::ARM64_H6, AArch64::H6},

277 {codeview::RegisterId::ARM64_H7, AArch64::H7},

278 {codeview::RegisterId::ARM64_H8, AArch64::H8},

279 {codeview::RegisterId::ARM64_H9, AArch64::H9},

280 {codeview::RegisterId::ARM64_H10, AArch64::H10},

281 {codeview::RegisterId::ARM64_H11, AArch64::H11},

282 {codeview::RegisterId::ARM64_H12, AArch64::H12},

283 {codeview::RegisterId::ARM64_H13, AArch64::H13},

284 {codeview::RegisterId::ARM64_H14, AArch64::H14},

285 {codeview::RegisterId::ARM64_H15, AArch64::H15},

286 {codeview::RegisterId::ARM64_H16, AArch64::H16},

287 {codeview::RegisterId::ARM64_H17, AArch64::H17},

288 {codeview::RegisterId::ARM64_H18, AArch64::H18},

289 {codeview::RegisterId::ARM64_H19, AArch64::H19},

290 {codeview::RegisterId::ARM64_H20, AArch64::H20},

291 {codeview::RegisterId::ARM64_H21, AArch64::H21},

292 {codeview::RegisterId::ARM64_H22, AArch64::H22},

293 {codeview::RegisterId::ARM64_H23, AArch64::H23},

294 {codeview::RegisterId::ARM64_H24, AArch64::H24},

295 {codeview::RegisterId::ARM64_H25, AArch64::H25},

296 {codeview::RegisterId::ARM64_H26, AArch64::H26},

297 {codeview::RegisterId::ARM64_H27, AArch64::H27},

298 {codeview::RegisterId::ARM64_H28, AArch64::H28},

299 {codeview::RegisterId::ARM64_H29, AArch64::H29},

300 {codeview::RegisterId::ARM64_H30, AArch64::H30},

301 {codeview::RegisterId::ARM64_H31, AArch64::H31},

302 };

303 for (const auto &I : RegMap)

304 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));

305}

308 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];

310 return Op.isReg() && FPR16.contains(Op.getReg());

311 });

312}

315 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];

317 return Op.isReg() && FPR128.contains(Op.getReg());

318 });

319}

322 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];

323 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID];

324 const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID];

325 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];

326 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID];

327

329 if (.isReg())

330 return false;

331 auto Reg = Op.getReg();

332 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) ||

333 FPR16.contains(Reg) || FPR8.contains(Reg);

334 };

335

337}

341 InitAArch64MCRegisterInfo(X, AArch64::LR);

343 return X;

344}

347 const Triple &TheTriple,

358 else

360

361

362 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);

365

366 return MAI;

367}

370 unsigned SyntaxVariant,

374 if (SyntaxVariant == 0)

376 if (SyntaxVariant == 1)

378

379 return nullptr;

380}

384 std::unique_ptr &&OW,

385 std::unique_ptr &&Emitter) {

387 std::move(Emitter), false,

388 true);

389}

503 return new AArch64MCInstrAnalysis(Info);

504}

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548 }

549

550

556}