AArch64Subtarget.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H

14#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H

31#define GET_SUBTARGETINFO_HEADER

32#include "AArch64GenSubtargetInfo.inc"

34namespace llvm {

35class GlobalValue;

36class StringRef;

39public:

42#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,

43#include "llvm/TargetParser/AArch64TargetParserDef.inc"

44#undef ARM_PROCESSOR_FAMILY

45 };

47protected:

55#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \

56 bool ATTRIBUTE = DEFAULT;

57#include "AArch64GenSubtargetInfo.inc"

103

104

110

111private:

112

113

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118 bool HasMinSize);

119

120

121 void initializeProperties(bool HasMinSize);

122

123public:

124

125

128 unsigned MinSVEVectorSizeInBitsOverride = 0,

129 unsigned MaxSVEVectorSizeInBitsOverride = 0,

131 bool HasMinSize = false);

132

133

134#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \

135 bool GETTER() const { return ATTRIBUTE; }

136#include "AArch64GenSubtargetInfo.inc"

137

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172

173

176 case AppleA14:

177 case AppleA15:

178 case AppleA16:

179 case AppleA17:

180 case AppleM4:

181 return true;

182 default:

183 return false;

184 }

185 }

186

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195

196

199 !hasSMEFA64() && hasSME() && hasSVE() ? 1024 : 0);

200 }

201

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206 return hasNEON() &&

208 }

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214 return hasSVE() &&

216 }

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241 return 0;

243 }

244

248 BitVector AllReservedX(AArch64::GPR64commonRegClass.getNumRegs());

251 return AllReservedX.count();

252 }

258

259

261 return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||

262 hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCmpCSel() ||

263 hasFuseCmpCSet() || hasFuseAdrpAdd() || hasFuseLiterals();

264 }

265

276 unsigned NumStridedMemAccesses,

277 unsigned NumPrefetches,

278 bool HasCall) const override {

280 }

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321 bool useAA() const override;

322

328

330 switch (TLInfo.getTargetMachine().getCodeModel()) {

332

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335 return true;

336 default:

337 return false;

338 }

339 }

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360 unsigned char

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377 switch (CC) {

386 return true;

387 default:

388 return false;

389 }

390 }

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401 unsigned Major = TT.getOSVersion().getMajor();

402 switch(TT.getOS()) {

403 default:

404 return false;

407 return Major < 15;

409 return Major < 8;

412 return Major < 12;

413 }

414 }

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420

423 "Tried to get SVE vector length without SVE support!");

425 }

426

429 "Tried to get SVE vector length without SVE support!");

431 }

432

433

434

437 "Tried to get SVE vector length without SVE support!");

440 return 0;

441 }

442

445 return false;

446

447

449 }

450

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467

470 return "#__chkstk_arm64ec";

471 return "__chkstk";

472 }

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484

485 std::optional<uint16_t>

487};

488}

489

490#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file describes how to lower LLVM calls to machine code calls.

This file describes how to lower LLVM inline asm to machine code INLINEASM.

Interface for Targets to specify which operations they can successfully select and how the others sho...

const AArch64RegisterInfo & getRegisterInfo() const

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

AArch64Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const TargetMachine &TM, bool LittleEndian, unsigned MinSVEVectorSizeInBitsOverride=0, unsigned MaxSVEVectorSizeInBitsOverride=0, bool IsStreaming=false, bool IsStreamingCompatible=false, bool HasMinSize=false)

This constructor initializes the data members to match that of the specified triple.

const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override

Definition AArch64Subtarget.h:138

bool isTargetWindows() const

Definition AArch64Subtarget.h:307

BitVector ReserveXRegisterForRA

Definition AArch64Subtarget.h:79

BitVector ReserveXRegister

Definition AArch64Subtarget.h:76

const CallLowering * getCallLowering() const override

const AArch64RegisterInfo * getRegisterInfo() const override

Definition AArch64Subtarget.h:148

bool isNeonAvailable() const

Returns true if the target has NEON and the function at runtime is known to have NEON enabled (e....

Definition AArch64Subtarget.h:205

bool isLRReservedForRA() const

Definition AArch64Subtarget.h:253

TailFoldingOpts DefaultSVETFOpts

Definition AArch64Subtarget.h:92

unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override

Definition AArch64Subtarget.h:275

BitVector CustomCallSavedXRegs

Definition AArch64Subtarget.h:82

bool addrSinkUsingGEPs() const override

Definition AArch64Subtarget.h:323

bool IsStreamingCompatible

Definition AArch64Subtarget.h:87

std::unique_ptr< InstructionSelector > InstSelector

Definition AArch64Subtarget.h:107

bool IsLittle

Definition AArch64Subtarget.h:84

ARMProcFamilyEnum ARMProcFamily

ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.

Definition AArch64Subtarget.h:49

ARMProcFamilyEnum

Definition AArch64Subtarget.h:40

@ Generic

Definition AArch64Subtarget.h:41

unsigned getMinimumJumpTableEntries() const

Definition AArch64Subtarget.h:294

std::unique_ptr< RegisterBankInfo > RegBankInfo

Definition AArch64Subtarget.h:109

unsigned GatherOverhead

Definition AArch64Subtarget.h:65

bool useSVEForFixedLengthVectors(EVT VT) const

Definition AArch64Subtarget.h:451

unsigned VScaleForTuning

Definition AArch64Subtarget.h:91

const AArch64InstrInfo * getInstrInfo() const override

Definition AArch64Subtarget.h:147

bool useSmallAddressing() const

Definition AArch64Subtarget.h:329

unsigned EpilogueVectorizationMinVF

Definition AArch64Subtarget.h:59

bool hasFusion() const

Return true if the CPU supports any kind of instruction fusion.

Definition AArch64Subtarget.h:260

AArch64SelectionDAGInfo TSInfo

Definition AArch64Subtarget.h:101

bool isTargetELF() const

Definition AArch64Subtarget.h:313

unsigned getMaximumJumpTableSize() const

Definition AArch64Subtarget.h:293

std::optional< unsigned > StreamingHazardSize

Definition AArch64Subtarget.h:88

AArch64FrameLowering FrameLowering

Definition AArch64Subtarget.h:99

bool isTargetDarwin() const

Definition AArch64Subtarget.h:304

bool enableEarlyIfConversion() const override

const InlineAsmLowering * getInlineAsmLowering() const override

unsigned MaxPrefetchIterationsAhead

Definition AArch64Subtarget.h:68

unsigned getCacheLineSize() const override

Definition AArch64Subtarget.h:271

bool isTargetILP32() const

Definition AArch64Subtarget.h:316

unsigned getVectorInsertExtractBaseCost() const

bool enableMachinePipeliner() const override

ARMProcFamilyEnum getProcFamily() const

Returns ARM processor family.

Definition AArch64Subtarget.h:168

std::unique_ptr< CallLowering > CallLoweringInfo

GlobalISel related APIs.

Definition AArch64Subtarget.h:105

std::optional< uint16_t > getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const

Compute the integer discriminator for a given BlockAddress constant, if blockaddress signing is enabl...

Align PrefLoopAlignment

Definition AArch64Subtarget.h:70

unsigned getGatherOverhead() const

Definition AArch64Subtarget.h:273

bool isXRegisterReservedForRA(size_t i) const

Definition AArch64Subtarget.h:246

unsigned getNumXRegisterReserved() const

Definition AArch64Subtarget.h:247

unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const

bool useAA() const override

bool isStreamingSVEAvailable() const

Returns true if the target has access to the streaming-compatible subset of SVE instructions.

Definition AArch64Subtarget.h:220

uint8_t VectorInsertExtractBaseCost

Definition AArch64Subtarget.h:61

const AArch64TargetLowering * getTargetLowering() const override

Definition AArch64Subtarget.h:144

Align getPrefLoopAlignment() const

Definition AArch64Subtarget.h:287

Align getPrefFunctionAlignment() const

Definition AArch64Subtarget.h:284

bool isTargetMachO() const

Definition AArch64Subtarget.h:314

unsigned getMaxBytesForLoopAlignment() const

Definition AArch64Subtarget.h:289

bool isNonStreamingSVEorSME2Available() const

Returns true if the target has access to either the full range of SVE instructions,...

Definition AArch64Subtarget.h:231

uint16_t PrefetchDistance

Definition AArch64Subtarget.h:66

bool supportsAddressTopByteIgnored() const

CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it.

unsigned getMaxInterleaveFactor() const

Definition AArch64Subtarget.h:269

void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override

bool isTargetAndroid() const

Definition AArch64Subtarget.h:308

Align PrefFunctionAlignment

Definition AArch64Subtarget.h:69

unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const override

This function is design to compatible with the function def in other targets and escape build error a...

Definition AArch64Subtarget.h:361

const Triple & getTargetTriple() const

Definition AArch64Subtarget.h:156

unsigned getStreamingHazardSize() const

Returns the size of memory region that if accessed by both the CPU and the SME unit could result in a...

Definition AArch64Subtarget.h:197

unsigned MinVectorRegisterBitWidth

Definition AArch64Subtarget.h:52

bool isStreamingCompatible() const

Returns true if the function has a streaming-compatible body.

Definition AArch64Subtarget.h:193

const char * getChkStkName() const

Definition AArch64Subtarget.h:468

bool isXRegCustomCalleeSaved(size_t i) const

Definition AArch64Subtarget.h:254

void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override

void mirFileLoaded(MachineFunction &MF) const override

Triple TargetTriple

TargetTriple - What processor and OS we're targeting.

Definition AArch64Subtarget.h:97

InstructionSelector * getInstructionSelector() const override

uint16_t MinPrefetchStride

Definition AArch64Subtarget.h:67

bool isSVEorStreamingSVEAvailable() const

Returns true if the target has access to either the full range of SVE instructions,...

Definition AArch64Subtarget.h:224

bool enableSubRegLiveness() const override

Definition AArch64Subtarget.h:159

uint16_t CacheLineSize

Definition AArch64Subtarget.h:62

TailFoldingOpts getSVETailFoldingDefaultOpts() const

Definition AArch64Subtarget.h:460

bool useSVEForFixedLengthVectors() const

Definition AArch64Subtarget.h:443

unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...

bool isLittleEndian() const

Definition AArch64Subtarget.h:302

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

unsigned MaxJumpTableSize

Definition AArch64Subtarget.h:73

unsigned getMinVectorRegisterBitWidth() const

Definition AArch64Subtarget.h:235

bool isWindowsArm64EC() const

Definition AArch64Subtarget.h:310

bool isStreaming() const

Returns true if the function has a streaming body.

Definition AArch64Subtarget.h:190

unsigned MinSVEVectorSizeInBits

Definition AArch64Subtarget.h:89

bool isX16X17Safer() const

Returns whether the operating system makes it safer to store sensitive values in x16 and x17 as oppos...

unsigned getSVEVectorSizeInBits() const

Definition AArch64Subtarget.h:435

bool isXRegisterReserved(size_t i) const

Definition AArch64Subtarget.h:245

unsigned getMaxPrefetchIterationsAhead() const override

Definition AArch64Subtarget.h:281

bool isTargetFuchsia() const

Definition AArch64Subtarget.h:309

bool useScalarIncVL() const

Returns true to use the addvl/inc/dec instructions, as opposed to separate add + cnt instructions.

bool useDFAforSMS() const override

Definition AArch64Subtarget.h:162

unsigned MinimumJumpTableEntries

Definition AArch64Subtarget.h:72

const LegalizerInfo * getLegalizerInfo() const override

bool enableMachineScheduler() const override

Definition AArch64Subtarget.h:157

unsigned getScatterOverhead() const

Definition AArch64Subtarget.h:272

bool enablePostRAScheduler() const override

Definition AArch64Subtarget.h:158

unsigned MaxSVEVectorSizeInBits

Definition AArch64Subtarget.h:90

bool EnableSubregLiveness

Definition AArch64Subtarget.h:94

std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override

unsigned getEpilogueVectorizationMinVF() const

Definition AArch64Subtarget.h:266

uint8_t MaxInterleaveFactor

Definition AArch64Subtarget.h:60

unsigned getMaxSVEVectorSizeInBits() const

Definition AArch64Subtarget.h:421

bool isCallingConvWin64(CallingConv::ID CC, bool IsVarArg) const

Definition AArch64Subtarget.h:376

unsigned getVScaleForTuning() const

Definition AArch64Subtarget.h:458

bool isTargetLinux() const

Definition AArch64Subtarget.h:306

unsigned ScatterOverhead

Definition AArch64Subtarget.h:64

unsigned getMinSVEVectorSizeInBits() const

Definition AArch64Subtarget.h:427

AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod(const MachineFunction &MF) const

Choose a method of checking LR before performing a tail call.

AArch64InstrInfo InstrInfo

Definition AArch64Subtarget.h:100

AArch64TargetLowering TLInfo

Definition AArch64Subtarget.h:102

const RegisterBankInfo * getRegBankInfo() const override

bool isTargetIOS() const

Definition AArch64Subtarget.h:305

std::unique_ptr< LegalizerInfo > Legalizer

Definition AArch64Subtarget.h:108

unsigned MaxBytesForLoopAlignment

Definition AArch64Subtarget.h:71

std::unique_ptr< InlineAsmLowering > InlineAsmLoweringInfo

Definition AArch64Subtarget.h:106

bool isAppleMLike() const

Returns true if the processor is an Apple M-series or aligned A-series (A14 or newer).

Definition AArch64Subtarget.h:174

bool isTargetCOFF() const

Definition AArch64Subtarget.h:312

bool IsStreaming

Definition AArch64Subtarget.h:86

bool isXRaySupported() const override

Definition AArch64Subtarget.h:187

bool isSVEAvailable() const

Returns true if the target has SVE and can use the full range of SVE instructions,...

Definition AArch64Subtarget.h:213

bool hasCustomCallingConv() const

Definition AArch64Subtarget.h:257

const AArch64FrameLowering * getFrameLowering() const override

Definition AArch64Subtarget.h:141

bool swiftAsyncContextIsDynamicallySet() const

Return whether FrameLowering should always set the "extended framepresent" bit in FP,...

Definition AArch64Subtarget.h:394

unsigned getPrefetchDistance() const override

Definition AArch64Subtarget.h:274

size_type count() const

count - Returns the number of bits which are set.

Holds all the information related to register banks.

Scheduling unit. This is a node in the scheduling DAG.

StringRef - Represent a constant reference to a string, i.e.

Primary interface to the complete machine description for the target machine.

Provide an instruction scheduling machine model to CodeGen passes.

Triple - Helper class for working with autoconf configuration names.

A Use represents the edge between a Value definition and its users.

AuthCheckMethod

Variants of check performed on an authenticated pointer.

static constexpr unsigned SVEBitsPerBlock

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Swift

Calling convention for Swift.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ PreserveNone

Used for runtime calls that preserves none general registers.

@ Win64

The C convention as implemented on Windows/x86-64 and AArch64.

@ SwiftTail

This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...

@ C

The default llvm calling convention, compatible with C.

This is an optimization pass for GlobalISel generic memory operations.

TailFoldingOpts

An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Lo...

This struct is a compact representation of a valid (non-zero power of two) alignment.

uint64_t getFixedSizeInBits() const

Return the size of the specified fixed width value type in bits.

bool isFixedLengthVector() const

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.

A region of an MBB for scheduling.