AArch64TargetMachine.cpp Source File (original) (raw)

55#include

57using namespace llvm;

60 cl::desc("Enable the CCMP formation pass"),

65 cl::desc("Enable the conditional branch tuning pass"),

69 "aarch64-enable-copy-propagation",

70 cl::desc("Enable the copy propagation with AArch64 copy instr"),

74 cl::desc("Enable the machine combiner pass"),

78 cl::desc("Suppress STP for AArch64"),

82 "aarch64-enable-simd-scalar",

83 cl::desc("Enable use of AdvSIMD scalar integer instructions"),

88 cl::desc("Enable the promote constant pass"),

92 "aarch64-enable-collect-loh",

93 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),

98 cl::desc("Enable the pass that removes dead"

99 " definitions and replaces stores to"

100 " them with stores to the zero"

101 " register"),

103

105 "aarch64-enable-copyelim",

106 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),

108

110 cl::desc("Enable the load/store pair"

111 " optimization pass"),

113

115 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,

116 cl::desc("Run SimplifyCFG after expanding atomic operations"

117 " to make use of cmpxchg flow-based information"),

119

122 cl::desc("Run early if-conversion"),

124

127 cl::desc("Enable the condition optimizer pass"),

129

132 cl::desc("Enable optimizations on complex GEPs"),

134

137 cl::desc("Enable select to branch optimizations"),

139

142 cl::desc("Relax out of range conditional branches"));

143

146 cl::desc("Use smallest entry possible for jump tables"));

147

148

151 cl::desc("Enable the global merge pass"));

152

155 cl::desc("Enable the loop data prefetch pass"),

157

159 "aarch64-enable-global-isel-at-O", cl::Hidden,

160 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),

162

165 cl::desc("Enable SVE intrinsic opts"),

167

171 cl::desc("Perform SME peephole optimization"));

172

175

178 cl::desc("Enable the AArch64 branch target pass"),

180

182 "aarch64-sve-vector-bits-max",

183 cl::desc("Assume SVE vector registers are at most this big, "

184 "with zero meaning no maximum size is assumed."),

186

188 "aarch64-sve-vector-bits-min",

189 cl::desc("Assume SVE vector registers are at least this big, "

190 "with zero meaning no minimum size is assumed."),

192

194 "force-streaming",

195 cl::desc("Force the use of streaming code for all functions"),

197

199 "force-streaming-compatible",

200 cl::desc("Force the use of streaming-compatible code for all functions"),

202

204

206 "aarch64-enable-gisel-ldst-prelegal",

207 cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"),

209

211 "aarch64-enable-gisel-ldst-postlegal",

212 cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"),

214

217 cl::desc("Enable sinking and folding of instruction copies"),

219

222 cl::desc("Enable Machine Pipeliner for AArch64"),

224

227 cl::desc("Enable new lowering for the SME ABI"),

229

282

284

285

286

287

288static std::unique_ptr createTLOF(const Triple &TT) {

289 if (TT.isOSBinFormatMachO())

290 return std::make_unique<AArch64_MachoTargetObjectFile>();

291 if (TT.isOSBinFormatCOFF())

292 return std::make_unique<AArch64_COFFTargetObjectFile>();

293

294 return std::make_unique<AArch64_ELFTargetObjectFile>();

295}

296

298 if (CPU.empty() && TT.isArm64e())

299 return "apple-a12";

300 return CPU;

301}

302

304 std::optionalReloc::Model RM) {

305

306 if (TT.isOSDarwin() || TT.isOSWindows())

308

309

310

313 return *RM;

314}

315

318 std::optionalCodeModel::Model CM, bool JIT) {

319 if (CM) {

323 "Only small, tiny and large code models are allowed on AArch64");

324 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF()) {

326 }

327 return *CM;

328 }

329

330

331

332

333

334

335 if (JIT && !TT.isOSWindows())

338}

339

340

341

345 std::optionalReloc::Model RM,

346 std::optionalCodeModel::Model CM,

348 bool LittleEndian)

356

357 if (TT.isOSBinFormatMachO()) {

360 }

361

363

364

365

366

367

368

370 }

371

372 if (this->Options.TLSSize == 0)

373 this->Options.TLSSize = 24;

376 this->Options.TLSSize > 32)

377

378 this->Options.TLSSize = 32;

380

381 this->Options.TLSSize = 24;

382

383

384

391 }

392

393

395

396

398

399

401

402

405}

406

408

411 Attribute CPUAttr = F.getFnAttribute("target-cpu");

412 Attribute TuneAttr = F.getFnAttribute("tune-cpu");

413 Attribute FSAttr = F.getFnAttribute("target-features");

414

418 bool HasMinSize = F.hasMinSize();

419

421 F.hasFnAttribute("aarch64_pstate_sm_enabled") ||

422 F.hasFnAttribute("aarch64_pstate_sm_body");

424 F.hasFnAttribute("aarch64_pstate_sm_compatible");

425

426 unsigned MinSVEVectorSize = 0;

427 unsigned MaxSVEVectorSize = 0;

428 if (F.hasFnAttribute(Attribute::VScaleRange)) {

432 } else {

435 }

436

437 assert(MinSVEVectorSize % 128 == 0 &&

438 "SVE requires vector length in multiples of 128!");

439 assert(MaxSVEVectorSize % 128 == 0 &&

440 "SVE requires vector length in multiples of 128!");

441 assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&

442 "Minimum SVE vector size should not be larger than its maximum!");

443

444

445 if (MaxSVEVectorSize != 0) {

446 MinSVEVectorSize = std::min(MinSVEVectorSize, MaxSVEVectorSize);

447 MaxSVEVectorSize = std::max(MinSVEVectorSize, MaxSVEVectorSize);

448 }

449

452 << MaxSVEVectorSize << "IsStreaming=" << IsStreaming

453 << "IsStreamingCompatible=" << IsStreamingCompatible

454 << CPU << TuneCPU << FS

455 << "HasMinSize=" << HasMinSize;

456

458 if () {

459

460

461

463 I = std::make_unique(

464 TargetTriple, CPU, TuneCPU, FS, *this, isLittle, MinSVEVectorSize,

465 MaxSVEVectorSize, IsStreaming, IsStreamingCompatible, HasMinSize);

466 }

467

468 if (IsStreaming && ->hasSME())

470

471 return I.get();

472}

473

480 if (ST.hasFusion())

482 return DAG;

483}

484

489 if (ST.hasFusion()) {

490

491

493 return DAG;

494 }

495

496 return DAG;

497}

498

507

508void AArch64leTargetMachine::anchor() { }

509

515

516void AArch64beTargetMachine::anchor() { }

517

523

524namespace {

525

526

528public:

534 }

535

538 }

539

540 void addIRPasses() override;

541 bool addPreISel() override;

542 void addCodeGenPrepare() override;

543 bool addInstSelector() override;

544 bool addIRTranslator() override;

545 void addPreLegalizeMachineIR() override;

546 bool addLegalizeMachineIR() override;

547 void addPreRegBankSelect() override;

548 bool addRegBankSelect() override;

549 bool addGlobalInstructionSelect() override;

550 void addMachineSSAOptimization() override;

551 bool addILPOpts() override;

552 void addPreRegAlloc() override;

553 void addPostRegAlloc() override;

554 void addPreSched2() override;

555 void addPreEmitPass() override;

556 void addPostBBSections() override;

557 void addPreEmitPass2() override;

558 bool addRegAssignAndRewriteOptimized() override;

559

560 std::unique_ptr getCSEConfig() const override;

561};

562

563}

564

566

567 PB.registerLateLoopOptimizationsEPCallback(

571 });

573 PB.registerPipelineEarlySimplificationEPCallback(

576 });

577}

578

583

585 return new AArch64PassConfig(*this, PM);

586}

587

588std::unique_ptr AArch64PassConfig::getCSEConfig() const {

590}

591

592void AArch64PassConfig::addIRPasses() {

593

594

596

597

601

602

603

604

607 .forwardSwitchCondToPhi(true)

608 .convertSwitchRangeToICmp(true)

609 .convertSwitchToLookupTable(true)

610 .needCanonicalLoops(false)

611 .hoistCommonInsts(true)

612 .sinkCommonInsts(true)));

613

614

615

616

617

623 }

624

626

627

628

630

631

633

634

636 }

637

639

642

645

646

649

650

654 }

655

657

658

659

661 }

662

663

664 if (TM->getTargetTriple().isOSWindows()) {

665 if (TM->getTargetTriple().isWindowsArm64EC())

667 else

669 }

670

671 if (TM->Options.JMCInstrument)

673}

674

675

676bool AArch64PassConfig::addPreISel() {

677

678

681

682

683

687 bool OnlyOptimizeForSize =

690

691

692

693

694

695 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();

697 MergeExternalByDefault));

698 }

699

700 return false;

701}

702

703void AArch64PassConfig::addCodeGenPrepare() {

707}

708

709bool AArch64PassConfig::addInstSelector() {

711

712

713

714 if (TM->getTargetTriple().isOSBinFormatELF() &&

717

718 return false;

719}

720

721bool AArch64PassConfig::addIRTranslator() {

723 return false;

724}

725

726void AArch64PassConfig::addPreLegalizeMachineIR() {

730 } else {

735 }

736}

737

738bool AArch64PassConfig::addLegalizeMachineIR() {

740 return false;

741}

742

743void AArch64PassConfig::addPreRegBankSelect() {

745 if (!IsOptNone) {

749 }

751}

752

753bool AArch64PassConfig::addRegBankSelect() {

755 return false;

756}

757

758bool AArch64PassConfig::addGlobalInstructionSelect() {

762 return false;

763}

764

765void AArch64PassConfig::addMachineSSAOptimization() {

768

771

772

774

777}

778

779bool AArch64PassConfig::addILPOpts() {

795 return true;

796}

797

798void AArch64PassConfig::addPreRegAlloc() {

801

802

806

807

810

811

813 }

816}

817

818void AArch64PassConfig::addPostRegAlloc() {

819

823

825

827}

828

829void AArch64PassConfig::addPreSched2() {

830

833

835

839 }

840

842

843

844

845

846

847

849

853 }

854}

855

856void AArch64PassConfig::addPreEmitPass() {

857

858

859

862

868

870

871 if (TM->getTargetTriple().isOSWindows()) {

872

874

876 }

877

879 TM->getTargetTriple().isOSBinFormatMachO())

881}

882

883void AArch64PassConfig::addPostBBSections() {

888

889

892

895}

896

897void AArch64PassConfig::addPreEmitPass2() {

898

899

901}

902

903bool AArch64PassConfig::addRegAssignAndRewriteOptimized() {

906}

907

914

919

925

cl::opt< bool > EnableHomogeneousPrologEpilog("homogeneous-prolog-epilog", cl::Hidden, cl::desc("Emit homogeneous prologue and epilogue for the size " "optimization (default = off)"))

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AArch64 branch target pass"), cl::init(true))

static cl::opt< bool > EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, cl::desc("Enable SVE intrinsic opts"), cl::init(true))

static cl::opt< bool > EnableAArch64CopyPropagation("aarch64-enable-copy-propagation", cl::desc("Enable the copy propagation with AArch64 copy instr"), cl::init(true), cl::Hidden)

static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))

static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to the zero" " register"), cl::init(true))

static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))

static cl::opt< bool > EnableSelectOpt("aarch64-select-opt", cl::Hidden, cl::desc("Enable select to branch optimizations"), cl::init(true))

static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableGISelLoadStoreOptPostLegal("aarch64-enable-gisel-ldst-postlegal", cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"), cl::init(false), cl::Hidden)

static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU)

Definition AArch64TargetMachine.cpp:297

static cl::opt< unsigned > SVEVectorBitsMinOpt("aarch64-sve-vector-bits-min", cl::desc("Assume SVE vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)

static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)

static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))

static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)

static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)

Definition AArch64TargetMachine.cpp:317

static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > ForceStreaming("force-streaming", cl::desc("Force the use of streaming code for all functions"), cl::init(false), cl::Hidden)

static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableGISelLoadStoreOptPreLegal("aarch64-enable-gisel-ldst-prelegal", cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableNewSMEABILowering("aarch64-new-sme-abi", cl::desc("Enable new lowering for the SME ABI"), cl::init(false), cl::Hidden)

static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))

static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)

static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))

static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))

static cl::opt< bool > EnableSMEPeepholeOpt("enable-aarch64-sme-peephole-opt", cl::init(true), cl::Hidden, cl::desc("Perform SME peephole optimization"))

static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))

static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)

static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)

static cl::opt< unsigned > SVEVectorBitsMaxOpt("aarch64-sve-vector-bits-max", cl::desc("Assume SVE vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)

static cl::opt< bool > ForceStreamingCompatible("force-streaming-compatible", cl::desc("Force the use of streaming-compatible code for all functions"), cl::init(false), cl::Hidden)

static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)

Definition AArch64TargetMachine.cpp:288

static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target()

Definition AArch64TargetMachine.cpp:231

static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)

This file a TargetTransformInfoImplBase conforming object specific to the AArch64 target machine.

static Reloc::Model getEffectiveRelocModel()

This file contains the simple types necessary to represent the attributes associated with functions a...

Provides analysis for continuously CSEing during GISel passes.

#define LLVM_EXTERNAL_VISIBILITY

static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))

This file declares the IRTranslator pass.

PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)

This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...

const GCNTargetMachine & getTM(const GCNSubtarget *STI)

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

Target-Independent Code Generator Pass Configuration Options pass.

This pass exposes codegen information to IR-level passes.

static std::unique_ptr< TargetLoweringObjectFile > createTLOF()

AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...

size_t clearLinkerOptimizationHints(const SmallPtrSetImpl< MachineInstr * > &MIs)

size_t clearLinkerOptimizationHints(const SmallPtrSetImpl< MachineInstr * > &MIs) const override

Remove all Linker Optimization Hints (LOH) associated with instructions in MIs and.

Definition AArch64TargetMachine.cpp:499

StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

Definition AArch64TargetMachine.cpp:908

void registerPassBuilderCallbacks(PassBuilder &PB) override

Allow the target to modify the pass pipeline.

Definition AArch64TargetMachine.cpp:565

const AArch64Subtarget * getSubtargetImpl() const =delete

yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override

Allocate and return a default initialized instance of the YAML representation for the MachineFunction...

Definition AArch64TargetMachine.cpp:916

ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override

Similar to createMachineScheduler but used when postRA machine scheduling is enabled.

Definition AArch64TargetMachine.cpp:486

~AArch64TargetMachine() override

std::unique_ptr< TargetLoweringObjectFile > TLOF

yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.

Definition AArch64TargetMachine.cpp:921

bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override

Parse out the target's MachineFunctionInfo from the YAML reprsentation.

Definition AArch64TargetMachine.cpp:926

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

Definition AArch64TargetMachine.cpp:584

void reset() override

Reset internal state.

Definition AArch64TargetMachine.cpp:283

AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT, bool IsLittleEndian)

Create an AArch64 architecture model.

Definition AArch64TargetMachine.cpp:342

ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...

Definition AArch64TargetMachine.cpp:475

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Return a TargetTransformInfo for a given function.

Definition AArch64TargetMachine.cpp:580

AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

Definition AArch64TargetMachine.cpp:518

AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

Definition AArch64TargetMachine.cpp:510

uint64_t getZExtValue() const

Get zero extended value.

Functions, function parameters, and return types can have attributes to indicate how they should be t...

LLVM_ABI StringRef getValueAsString() const

Return the attribute's value as a string.

bool isValid() const

Return true if the attribute is any kind of attribute.

CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOptLevel OL)

This class represents a range of values.

LLVM_ABI APInt getUnsignedMin() const

Return the smallest unsigned value contained in the ConstantRange.

LLVM_ABI APInt getUnsignedMax() const

Return the largest unsigned value contained in the ConstantRange.

Lightweight error class with error context and mandatory checking.

This pass is responsible for selecting generic machine instructions to target-specific instructions.

This pass implements the localization mechanism described at the top of this file.

Pass to replace calls to ifuncs with indirect calls.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

static LLVM_ABI const OptimizationLevel O0

Disable as many optimizations as possible.

This class provides access to building LLVM's passes.

LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v< PassT, PassManager > > addPass(PassT &&Pass)

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

This pass implements the reg bank selector pass used in the GlobalISel pipeline.

Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...

Represents a range in source code.

A ScheduleDAG for scheduling lists of MachineInstr.

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...

StringRef - Represent a constant reference to a string, i.e.

CodeGenOptLevel getOptLevel() const

Returns the optimization level: None, Less, Default, or Aggressive.

void setSupportsDebugEntryValues(bool Enable)

Triple TargetTriple

Triple string, CPU name, and target feature strings the TargetMachine instance is created with.

const Triple & getTargetTriple() const

void setMachineOutliner(bool Enable)

void setCFIFixup(bool Enable)

void setSupportsDefaultOutlining(bool Enable)

void setGlobalISelAbort(GlobalISelAbortMode Mode)

std::unique_ptr< const MCSubtargetInfo > STI

void setGlobalISel(bool Enable)

CodeModel::Model getCodeModel() const

Returns the code model.

void resetTargetOptions(const Function &F) const

Reset the target options based on the function's attributes.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

unsigned TLSSize

Bit size of immediate TLS offsets (0 == use the default).

unsigned NoTrapAfterNoreturn

Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...

unsigned TrapUnreachable

Emit target-specific trap instruction for 'unreachable' IR instructions.

Target-Independent Code Generator Pass Configuration Options.

virtual void addCodeGenPrepare()

Add pass to prepare the LLVM IR for code generation.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

virtual void addMachineSSAOptimization()

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

virtual bool addRegAssignAndRewriteOptimized()

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

A raw_ostream that writes to an SmallVector or SmallString.

Interfaces for registering analysis passes, producing common pass manager configurations,...

@ C

The default llvm calling convention, compatible with C.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

ScheduleDAGMILive * createSchedLive(MachineSchedContext *C)

Create the standard converging machine scheduler.

FunctionPass * createAArch64PreLegalizerCombiner()

void initializeLDTLSCleanupPass(PassRegistry &)

LLVM_ABI FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)

FunctionPass * createSMEABIPass()

void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)

void initializeMachineSMEABIPass(PassRegistry &)

FunctionPass * createAArch64PostSelectOptimize()

LLVM_ABI ModulePass * createJMCInstrumenterPass()

JMC instrument pass.

void initializeAArch64SpeculationHardeningPass(PassRegistry &)

void initializeAArch64PostLegalizerLoweringPass(PassRegistry &)

FunctionPass * createAArch64RedundantCopyEliminationPass()

FunctionPass * createAArch64StackTaggingPreRAPass()

LLVM_ABI FunctionPass * createTypePromotionLegacyPass()

Create IR Type Promotion pass.

void initializeAArch64PostLegalizerCombinerPass(PassRegistry &)

FunctionPass * createAArch64MIPeepholeOptPass()

void initializeAArch64AdvSIMDScalarPass(PassRegistry &)

void initializeAArch64PostCoalescerPass(PassRegistry &)

FunctionPass * createMachineSMEABIPass(CodeGenOptLevel)

LLVM_ABI FunctionPass * createSelectOptimizePass()

This pass converts conditional moves to conditional jumps when profitable.

LLVM_ABI Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false, bool MergeConstantByDefault=false, bool MergeConstAggressiveByDefault=false)

GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...

FunctionPass * createAArch64PostCoalescerPass()

void initializeAArch64PromoteConstantPass(PassRegistry &)

FunctionPass * createFalkorMarkStridedAccessesPass()

Target & getTheAArch64beTarget()

FunctionPass * createAArch64PointerAuthPass()

FunctionPass * createFalkorHWPFFixPass()

void initializeAArch64RedundantCondBranchPass(PassRegistry &)

LLVM_ABI char & PostRASchedulerID

PostRAScheduler - This pass performs post register allocation scheduling.

FunctionPass * createAArch64O0PreLegalizerCombiner()

FunctionPass * createAArch64A57FPLoadBalancing()

FunctionPass * createAArch64CondBrTuning()

LLVM_ABI std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)

void initializeAArch64Arm64ECCallLoweringPass(PassRegistry &)

void initializeSMEABIPass(PassRegistry &)

LLVM_ABI char & PostMachineSchedulerID

PostMachineScheduler - This pass schedules machine instructions postRA.

LLVM_ABI char & PeepholeOptimizerLegacyID

PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...

LLVM_ABI Pass * createLICMPass()

Target & getTheAArch64leTarget()

FunctionPass * createAArch64DeadRegisterDefinitions()

LLVM_ABI char & EarlyIfConverterLegacyID

EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.

FunctionPass * createSMEPeepholeOptPass()

FunctionPass * createAArch64PostLegalizerLowering()

ThinOrFullLTOPhase

This enumerates the LLVM full LTO or ThinLTO optimization phases.

PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & > LoopPassManager

The Loop pass manager.

LLVM_ABI char & MachineCombinerID

This pass performs instruction combining using trace metrics to estimate critical-path and resource d...

void initializeAArch64AsmPrinterPass(PassRegistry &)

static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)

FunctionPass * createAArch64CompressJumpTablesPass()

Target & getTheAArch64_32Target()

FunctionPass * createAArch64ConditionalCompares()

ScheduleDAGMI * createSchedPostRA(MachineSchedContext *C)

Create a generic scheduler with no vreg liveness or DAG mutation passes.

LLVM_ABI char & BranchRelaxationPassID

BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...

void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)

void initializeAArch64ExpandPseudoPass(PassRegistry &)

void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)

void initializeAArch64StackTaggingPass(PassRegistry &)

FunctionPass * createAArch64ExpandPseudoPass()

Returns an instance of the pseudo instruction expansion pass.

LLVM_ABI FunctionPass * createKCFIPass()

Lowers KCFI operand bundles for indirect calls.

std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()

Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64TargetMa...

LLVM_ABI FunctionPass * createComplexDeinterleavingPass(const TargetMachine *TM)

This pass implements generation of target-specific intrinsics to support handling of complex number a...

PassManager< Module > ModulePassManager

Convenience typedef for a pass manager over modules.

ModulePass * createAArch64Arm64ECCallLoweringPass()

LLVM_ABI std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)

If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...

LLVM_ABI FunctionPass * createLoopDataPrefetchPass()

FunctionPass * createAArch64SIMDInstrOptPass()

Returns an instance of the high cost ASIMD instruction replacement optimization pass.

void initializeSMEPeepholeOptPass(PassRegistry &)

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

FunctionPass * createAArch64StorePairSuppressPass()

FunctionPass * createAArch64ConditionOptimizerPass()

ModulePass * createSVEIntrinsicOptsPass()

void initializeAArch64CompressJumpTablesPass(PassRegistry &)

void initializeAArch64SLSHardeningPass(PassRegistry &)

FunctionPass * createAArch64CollectLOHPass()

LLVM_ABI ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)

Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...

CodeGenOptLevel

Code generation optimization level.

FunctionPass * createAArch64LoadStoreOptimizationPass()

createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass.

void initializeAArch64StackTaggingPreRAPass(PassRegistry &)

LLVM_ABI FunctionPass * createCFGuardLongjmpPass()

Creates CFGuard longjmp target identification pass.

void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)

LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key

Target & getTheARM64_32Target()

FunctionPass * createAArch64PostLegalizerCombiner(bool IsOptNone)

void initializeAArch64StorePairSuppressPass(PassRegistry &)

void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &)

LLVM_ABI FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)

LLVM_ABI FunctionPass * createInterleavedAccessPass()

InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...

LLVM_ABI void initializeGlobalISel(PassRegistry &)

Initialize all passes linked into the GlobalISel library.

LLVM_ABI void initializeKCFIPass(PassRegistry &)

FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOptLevel OptLevel)

createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG,...

void initializeAArch64CondBrTuningPass(PassRegistry &)

LLVM_ABI char & MachinePipelinerID

This pass performs software pipelining on machine instructions.

void initializeAArch64MIPeepholeOptPass(PassRegistry &)

FunctionPass * createAArch64SLSHardeningPass()

FunctionPass * createAArch64BranchTargetsPass()

Target & getTheARM64Target()

LLVM_ABI std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)

If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...

void initializeFalkorHWPFFixPass(PassRegistry &)

LLVM_ABI FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)

void initializeAArch64BranchTargetsPass(PassRegistry &)

FunctionPass * createCFGuardCheckPass()

Insert Control FLow Guard checks on indirect function calls.

void initializeAArch64A53Fix835769Pass(PassRegistry &)

LLVM_ABI FunctionPass * createEHContGuardTargetsPass()

Creates Windows EH Continuation Guard target identification pass.

ModulePass * createAArch64LowerHomogeneousPrologEpilogPass()

void initializeAArch64LoadStoreOptPass(PassRegistry &)

void initializeAArch64SIMDInstrOptPass(PassRegistry &)

void initializeAArch64PostSelectOptimizePass(PassRegistry &)

void initializeAArch64CollectLOHPass(PassRegistry &)

FunctionPass * createAArch64StackTaggingPass(bool IsOptNone)

void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &)

void initializeAArch64ConditionOptimizerPass(PassRegistry &)

void initializeAArch64ConditionalComparesPass(PassRegistry &)

LLVM_ABI FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

FunctionPass * createAArch64CleanupLocalDynamicTLSPass()

BumpPtrAllocatorImpl<> BumpPtrAllocator

The standard BumpPtrAllocator which just uses the default template parameters.

ModulePass * createAArch64PromoteConstantPass()

LLVM_ABI FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)

LLVM_ABI MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)

FunctionPass * createAArch64AdvSIMDScalar()

FunctionPass * createAArch64RedundantCondBranchPass()

void initializeAArch64DAGToDAGISelLegacyPass(PassRegistry &)

FunctionPass * createAArch64SpeculationHardeningPass()

Returns an instance of the pseudo instruction expansion pass.

void initializeSVEIntrinsicOptsPass(PassRegistry &)

void initializeAArch64PointerAuthPass(PassRegistry &)

void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)

LLVM_ABI FunctionPass * createInterleavedLoadCombinePass()

InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...

FunctionPass * createAArch64A53Fix835769()

LLVM_ABI void reportFatalUsageError(Error Err)

Report a fatal error that does not indicate a bug in LLVM.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

static FuncInfoTy * create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)

Factory function: default behavior is to call new using the supplied allocator.

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...

RegisterTargetMachine - Helper template for registering a target machine implementation,...

Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.