AMDGPU.h Source File (original) (raw)

10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H

11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H

19namespace llvm {

21class AMDGPUTargetMachine;

22class GCNTargetMachine;

23class TargetMachine;

72};

75 : PassInfoMixin {

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265 : TM(TM), ScanImpl(ScanImpl) {}

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282 bool GlobalOpt;

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338 : TM(TM), Options(Options) {};

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466namespace AMDGPU {

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483 static const bool ASAliasRules[10][10] = {

484

485 {true, true, false, true, true, true, true, true, true, true},

486 {true, true, false, false, true, false, true, true, true, true},

487 {false, false, true, false, false, false, false, false, false, false},

488 {true, false, false, true, false, false, false, false, false, false},

489 {true, true, false, false, false, false, true, true, true, true},

490 {true, false, false, false, false, true, false, false, false, false},

491 {true, true, false, false, true, false, false, true, true, true},

492 {true, true, false, false, true, false, true, true, true, true},

493 {true, true, false, false, true, false, true, true, true, true},

494 {true, true, false, false, true, false, true, true, true, true},

495 };

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498 return ASAliasRules[AS1][AS2];

499}

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501}

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503}

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505#endif

AMDGPU address space definition.

This header defines various interfaces for pass management in LLVM.

AMDGPUAnnotateUniformValuesPass()

PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)

PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)

AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options={})

PreservedAnalyses run(Function &, FunctionAnalysisManager &)

AMDGPUCodeGenPreparePass(TargetMachine &TM)

AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM)

PreservedAnalyses run(Function &, FunctionAnalysisManager &)

AMDGPULowerKernelArgumentsPass(TargetMachine &TM)

PreservedAnalyses run(Function &, FunctionAnalysisManager &)

PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)

AMDGPURewriteUndefForPHIPass()=default

A container for analyses that lazily runs them and caches their results.

FunctionPass class - This class is used to implement most global optimizations.

ImmutablePass class - This class is used to provide information that does not need to be run.

ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...

A Module instance is used to store all the information related to an LLVM module.

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

Pass interface - Implemented by all 'passes'.

A set of analyses that are preserved following a run of a transformation pass.

SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM)

PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

SILowerI1CopiesPass()=default

Primary interface to the complete machine description for the target machine.

static bool addrspacesMayAlias(unsigned AS1, unsigned AS2)

This is an optimization pass for GlobalISel generic memory operations.

void initializeSIFormMemoryClausesPass(PassRegistry &)

ImmutablePass * createAMDGPUAAWrapperPass()

char & SIAnnotateControlFlowLegacyPassID

FunctionPass * createAMDGPUSetWavePriorityPass()

char & AMDGPUCtorDtorLoweringLegacyPassID

void initializeGCNCreateVOPDPass(PassRegistry &)

char & AMDGPUPreloadKernArgPrologLegacyID

char & AMDGPUAnnotateKernelFeaturesID

char & GCNPreRAOptimizationsID

void initializeGCNPreRAOptimizationsPass(PassRegistry &)

void initializeGCNRewritePartialRegUsesPass(llvm::PassRegistry &)

char & SIMemoryLegalizerID

void initializeAMDGPUAttributorLegacyPass(PassRegistry &)

FunctionPass * createSIAnnotateControlFlowLegacyPass()

Create the annotation pass.

FunctionPass * createSIModeRegisterPass()

void initializeAMDGPUAAWrapperPassPass(PassRegistry &)

void initializeSIShrinkInstructionsLegacyPass(PassRegistry &)

ModulePass * createAMDGPULowerBufferFatPointersPass()

char & SIShrinkInstructionsLegacyID

void initializeSIModeRegisterPass(PassRegistry &)

ModulePass * createAMDGPUCtorDtorLoweringLegacyPass()

char & AMDGPUImageIntrinsicOptimizerID

ModulePass * createAMDGPUSwLowerLDSLegacyPass(const AMDGPUTargetMachine *TM=nullptr)

void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &)

char & AMDGPUPromoteKernelArgumentsID

FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)

char & GCNRewritePartialRegUsesID

FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)

void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &)

FunctionPass * createAMDGPURewriteOutArgumentsPass()

void initializeGCNPreRALongBranchRegPass(PassRegistry &)

void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &)

char & AMDGPUResourceUsageAnalysisID

FunctionPass * createSIWholeQuadModePass()

void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &)

char & SIOptimizeExecMaskingLegacyID

FunctionPass * createSILoadStoreOptimizerLegacyPass()

ModulePass * createAMDGPULowerKernelAttributesPass()

ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)

void initializeSIPreEmitPeepholePass(PassRegistry &)

char & AMDGPUPromoteAllocaToVectorID

void initializeSIFoldOperandsLegacyPass(PassRegistry &)

char & SILoadStoreOptimizerLegacyID

char & SILowerWWMCopiesID

ModulePass * createAMDGPUUnifyMetadataPass()

void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &)

void initializeSILowerWWMCopiesPass(PassRegistry &)

FunctionPass * createSIPeepholeSDWALegacyPass()

void initializeGCNNSAReassignPass(PassRegistry &)

void initializeAMDGPUOpenCLEnqueuedBlockLoweringLegacyPass(PassRegistry &)

void initializeSIInsertWaitcntsPass(PassRegistry &)

char & SIFormMemoryClausesID

char & AMDGPURemoveIncompatibleFunctionsID

void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &)

void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &)

void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &)

void initializeAMDGPURegBankCombinerPass(PassRegistry &)

char & AMDGPUGlobalISelDivergenceLoweringID

void initializeSILateBranchLoweringPass(PassRegistry &)

FunctionPass * createSIFoldOperandsLegacyPass()

FunctionPass * createAMDGPUPromoteAllocaToVector()

char & AMDGPUUnifyDivergentExitNodesID

char & SIInsertWaitcntsID

FunctionPass * createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy)

FunctionPass * createAMDGPUPreloadKernArgPrologLegacyPass()

char & AMDGPUPrintfRuntimeBindingID

char & SIOptimizeVGPRLiveRangeLegacyID

void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)

void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)

void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)

char & SILateBranchLoweringPassID

char & AMDGPUSwLowerLDSLegacyPassID

FunctionPass * createGCNPreRAOptimizationsPass()

void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)

void initializeSIPostRABundlerPass(PassRegistry &)

void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)

char & GCNDPPCombineLegacyID

Pass * createAMDGPUAttributorLegacyPass()

void initializeSIWholeQuadModePass(PassRegistry &)

FunctionPass * createAMDGPULowerKernelArgumentsPass()

char & AMDGPUInsertDelayAluID

Pass * createAMDGPUAnnotateKernelFeaturesPass()

char & SIOptimizeExecMaskingPreRAID

char & AMDGPULowerModuleLDSLegacyPassID

void initializeSIInsertHardClausesPass(PassRegistry &)

FunctionPass * createSIPostRABundlerPass()

FunctionPass * createSIFormMemoryClausesPass()

void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)

FunctionPass * createSIPreAllocateWWMRegsLegacyPass()

Pass * createAMDGPUStructurizeCFGPass()

CodeGenOptLevel

Code generation optimization level.

char & AMDGPULowerBufferFatPointersID

char & AMDGPURegBankSelectID

void initializeAMDGPUReserveWWMRegsPass(PassRegistry &)

ModulePass * createAMDGPUPrintfRuntimeBinding()

void initializeSIMemoryLegalizerPass(PassRegistry &)

char & AMDGPUUnifyMetadataID

void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &)

void initializeSILowerControlFlowLegacyPass(PassRegistry &)

char & SIPreAllocateWWMRegsLegacyID

ModulePass * createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM=nullptr)

void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)

char & AMDGPUReserveWWMRegsID

FunctionPass * createAMDGPUPromoteAlloca()

char & SIPreEmitPeepholeID

ModulePass * createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *)

void initializeGCNRegPressurePrinterPass(PassRegistry &)

char & AMDGPURewriteOutArgumentsID

void initializeSILowerI1CopiesLegacyPass(PassRegistry &)

char & SILowerSGPRSpillsLegacyID

void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)

char & SILowerControlFlowLegacyID

char & AMDGPUPromoteAllocaID

FunctionPass * createAMDGPUCodeGenPreparePass()

void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &)

FunctionPass * createAMDGPUReserveWWMRegsPass()

ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringLegacyPass()

FunctionPass * createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel)

This pass converts a legalized DAG into a AMDGPU-specific.

void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &)

void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &)

void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &)

char & AMDGPUAnnotateUniformValuesLegacyPassID

void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)

char & AMDGPULowerKernelAttributesID

FunctionPass * createAMDGPURegBankSelectPass()

char & GCNRegPressurePrinterID

FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)

FunctionPass * createAMDGPURegBankLegalizePass()

void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)

void initializeAMDGPUMarkLastScratchLoadPass(PassRegistry &)

FunctionPass * createSIOptimizeVGPRLiveRangeLegacyPass()

ImmutablePass * createAMDGPUExternalAAWrapperPass()

void initializeAMDGPUCodeGenPreparePass(PassRegistry &)

FunctionPass * createAMDGPURewriteUndefForPHILegacyPass()

void initializeSIOptimizeExecMaskingLegacyPass(PassRegistry &)

FunctionPass * createSILowerI1CopiesLegacyPass()

char & AMDGPULateCodeGenPrepareLegacyID

void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)

char & SIInsertHardClausesID

void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)

char & SIFixSGPRCopiesLegacyID

void initializeGCNDPPCombineLegacyPass(PassRegistry &)

char & SIPeepholeSDWALegacyID

char & SIFoldOperandsLegacyID

char & AMDGPUAtomicOptimizerID

char & SILowerI1CopiesLegacyID

void initializeAMDGPUPreloadKernArgPrologLegacyPass(PassRegistry &)

FunctionPass * createLowerWWMCopiesPass()

char & AMDGPUOpenCLEnqueuedBlockLoweringLegacyID

FunctionPass * createAMDGPUGlobalISelDivergenceLoweringPass()

FunctionPass * createSIMemoryLegalizerPass()

void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &)

void initializeSIOptimizeVGPRLiveRangeLegacyPass(PassRegistry &)

void initializeSIPeepholeSDWALegacyPass(PassRegistry &)

char & AMDGPURegBankLegalizeID

void initializeAMDGPURegBankLegalizePass(PassRegistry &)

void initializeAMDGPURegBankSelectPass(PassRegistry &)

FunctionPass * createAMDGPULateCodeGenPrepareLegacyPass()

char & AMDGPURewriteUndefForPHILegacyPassID

FunctionPass * createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *)

void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)

void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &)

FunctionPass * createSIInsertWaitcntsPass()

FunctionPass * createAMDGPUAnnotateUniformValuesLegacy()

FunctionPass * createSIOptimizeExecMaskingPreRAPass()

FunctionPass * createGCNDPPCombinePass()

FunctionPass * createSIShrinkInstructionsLegacyPass()

AnalysisManager< Module > ModuleAnalysisManager

Convenience typedef for the Module analysis manager.

char & AMDGPUMarkLastScratchLoadID

void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &)

void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)

void initializeAMDGPUPromoteAllocaPass(PassRegistry &)

void initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(PassRegistry &)

void initializeAMDGPUInsertDelayAluPass(PassRegistry &)

void initializeAMDGPUUnifyMetadataPass(PassRegistry &)

FunctionPass * createSIFixControlFlowLiveIntervalsPass()

char & AMDGPULowerKernelArgumentsID

void initializeAMDGPUAlwaysInlinePass(PassRegistry &)

char & AMDGPUCodeGenPrepareID

void initializeAMDGPUSetWavePriorityPass(PassRegistry &)

FunctionPass * createSIFixSGPRCopiesLegacyPass()

char & AMDGPUPerfHintAnalysisLegacyID

FunctionPass * createAMDGPUPromoteKernelArgumentsPass()

char & GCNPreRALongBranchRegID

void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &)

void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)

AMDGPUAlwaysInlinePass(bool GlobalOpt=true)

PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)

PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)

AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)

PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)

AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM)

PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)

AMDGPULowerBufferFatPointersPass(const TargetMachine &TM)

PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)

PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)

AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_)

const AMDGPUTargetMachine & TM

PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)

AMDGPUSimplifyLibCallsPass()

PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)

const AMDGPUTargetMachine & TM

PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)

AMDGPUSwLowerLDSPass(const AMDGPUTargetMachine &TM_)

PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)

A CRTP mix-in to automatically provide informational APIs needed for passes.