#include #include #include "AMDGPUGenSearchableTables.inc"">

LLVM: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h File Reference (original) (raw)

#include "[AMDGPUSubtarget.h](AMDGPUSubtarget%5F8h%5Fsource.html)"
#include "[SIDefines.h](SIDefines%5F8h%5Fsource.html)"
#include "[llvm/IR/CallingConv.h](CallingConv%5F8h%5Fsource.html)"
#include "[llvm/IR/InstrTypes.h](InstrTypes%5F8h%5Fsource.html)"
#include "[llvm/IR/Module.h](IR%5F2Module%5F8h%5Fsource.html)"
#include "[llvm/Support/Alignment.h](Alignment%5F8h%5Fsource.html)"
#include <array>
#include <functional>
#include <utility>
#include "AMDGPUGenSearchableTables.inc"

Enumerations

enum

{ llvm::AMDGPU::AMDHSA_COV4 = 4 , llvm::AMDGPU::AMDHSA_COV5 = 5 , llvm::AMDGPU::AMDHSA_COV6 = 6 }

enum class

llvm::AMDGPU::FPType { llvm::AMDGPU::None, llvm::AMDGPU::FP4, llvm::AMDGPU::FP8 }

enum

{ llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG = 96 , llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS = 16 }

enum class

llvm::AMDGPU::IsaInfo::TargetIDSetting { llvm::AMDGPU::IsaInfo::Unsupported, llvm::AMDGPU::IsaInfo::Any, llvm::AMDGPU::IsaInfo::Off, llvm::AMDGPU::IsaInfo::On }

enum

llvm::AMDGPU::VOPD::Component : unsigned {
llvm::AMDGPU::VOPD::DST = 0 , llvm::AMDGPU::VOPD::SRC0, llvm::AMDGPU::VOPD::SRC1, llvm::AMDGPU::VOPD::SRC2,
llvm::AMDGPU::VOPD::DST_NUM = 1 , llvm::AMDGPU::VOPD::MAX_SRC_NUM = 3 , llvm::AMDGPU::VOPD::MAX_OPR_NUM = DST_NUM + MAX_SRC_NUM
}

enum

llvm::AMDGPU::VOPD::ComponentIndex : unsigned { llvm::AMDGPU::VOPD::X = 0 , llvm::AMDGPU::VOPD::Y = 1 }

enum

llvm::AMDGPU::VOPD::ComponentKind : unsigned { llvm::AMDGPU::VOPD::SINGLE = 0 , llvm::AMDGPU::VOPD::COMPONENT_X, llvm::AMDGPU::VOPD::COMPONENT_Y, llvm::AMDGPU::VOPD::MAX = COMPONENT_Y }

Functions

llvm::AMDGPU::isHsaAbi (const MCSubtargetInfo &STI)

llvm::AMDGPU::getAMDHSACodeObjectVersion (const Module &M)

llvm::AMDGPU::getAMDHSACodeObjectVersion (unsigned ABIVersion)

llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion ()

llvm::AMDGPU::getELFABIVersion (const Triple &T, unsigned CodeObjectVersion)

llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion)

llvm::AMDGPU::getHostcallImplicitArgPosition (unsigned CodeObjectVersion)

llvm::AMDGPU::getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion)

llvm::AMDGPU::getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion)

llvm::AMDGPU::IsaInfo::getWavefrontSize (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getLocalMemorySize (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getAddressableLocalMemorySize (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getEUsPerCU (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)

llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)

llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)

llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)

llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)

llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)

llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed)

llvm::AMDGPU::IsaInfo::getNumSGPRBlocks (const MCSubtargetInfo *STI, unsigned NumSGPRs)

llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)

llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)

llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getAddressableNumArchVGPRs (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const MCSubtargetInfo *STI)

llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)

llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)

llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs (const MCSubtargetInfo *STI, unsigned NumVGPRs)

llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs (unsigned NumVGPRs, unsigned Granule, unsigned MaxWaves, unsigned TotalNumVGPRs)

llvm::AMDGPU::IsaInfo::getOccupancyWithNumSGPRs (unsigned SGPRs, unsigned MaxWaves, AMDGPUSubtarget::Generation Gen)

llvm::AMDGPU::IsaInfo::getEncodedNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)

llvm::AMDGPU::IsaInfo::getAllocatedNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)

LLVM_READONLY int16_t

llvm::AMDGPU::getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)

LLVM_READONLY bool

llvm::AMDGPU::hasNamedOperand (uint64_t Opcode, uint64_t NamedIdx)

LLVM_READONLY int

llvm::AMDGPU::getSOPPWithRelaxation (uint16_t Opcode)

const MIMGBaseOpcodeInfo *

llvm::AMDGPU::getMIMGBaseOpcode (unsigned Opc)

LLVM_READONLY const MIMGBaseOpcodeInfo *

llvm::AMDGPU::getMIMGBaseOpcodeInfo (unsigned BaseOpcode)

LLVM_READONLY const MIMGDimInfo *

llvm::AMDGPU::getMIMGDimInfo (unsigned DimEnum)

LLVM_READONLY const MIMGDimInfo *

llvm::AMDGPU::getMIMGDimInfoByEncoding (uint8_t DimEnc)

LLVM_READONLY const MIMGDimInfo *

llvm::AMDGPU::getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)

LLVM_READONLY const MIMGLZMappingInfo *

llvm::AMDGPU::getMIMGLZMappingInfo (unsigned L)

LLVM_READONLY const MIMGMIPMappingInfo *

llvm::AMDGPU::getMIMGMIPMappingInfo (unsigned MIP)

LLVM_READONLY const MIMGBiasMappingInfo *

llvm::AMDGPU::getMIMGBiasMappingInfo (unsigned Bias)

LLVM_READONLY const MIMGOffsetMappingInfo *

llvm::AMDGPU::getMIMGOffsetMappingInfo (unsigned Offset)

LLVM_READONLY const MIMGG16MappingInfo *

llvm::AMDGPU::getMIMGG16MappingInfo (unsigned G)

int

llvm::AMDGPU::getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)

int

llvm::AMDGPU::getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)

llvm::AMDGPU::getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)

LLVM_READONLY const MIMGInfo *

llvm::AMDGPU::getMIMGInfo (unsigned Opc)

int

llvm::AMDGPU::getMTBUFBaseOpcode (unsigned Opc)

int

llvm::AMDGPU::getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)

int

llvm::AMDGPU::getMTBUFElements (unsigned Opc)

llvm::AMDGPU::getMTBUFHasVAddr (unsigned Opc)

llvm::AMDGPU::getMTBUFHasSrsrc (unsigned Opc)

llvm::AMDGPU::getMTBUFHasSoffset (unsigned Opc)

int

llvm::AMDGPU::getMUBUFBaseOpcode (unsigned Opc)

int

llvm::AMDGPU::getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)

int

llvm::AMDGPU::getMUBUFElements (unsigned Opc)

llvm::AMDGPU::getMUBUFHasVAddr (unsigned Opc)

llvm::AMDGPU::getMUBUFHasSrsrc (unsigned Opc)

llvm::AMDGPU::getMUBUFHasSoffset (unsigned Opc)

llvm::AMDGPU::getMUBUFIsBufferInv (unsigned Opc)

llvm::AMDGPU::getMUBUFTfe (unsigned Opc)

llvm::AMDGPU::getSMEMIsBuffer (unsigned Opc)

llvm::AMDGPU::getVOP1IsSingle (unsigned Opc)

llvm::AMDGPU::getVOP2IsSingle (unsigned Opc)

llvm::AMDGPU::getVOP3IsSingle (unsigned Opc)

llvm::AMDGPU::isVOPC64DPP (unsigned Opc)

llvm::AMDGPU::isVOPCAsmOnly (unsigned Opc)

llvm::AMDGPU::getMAIIsDGEMM (unsigned Opc)

Returns true if MAI operation is a double precision GEMM.

llvm::AMDGPU::getMAIIsGFX940XDL (unsigned Opc)

llvm::AMDGPU::getVOPDEncodingFamily (const MCSubtargetInfo &ST)

CanBeVOPD

llvm::AMDGPU::getCanBeVOPD (unsigned Opc)

llvm::AMDGPU::mfmaScaleF8F6F4FormatToNumRegs (unsigned EncodingVal)

const MFMA_F8F6F4_Info *

llvm::AMDGPU::getMFMA_F8F6F4_WithFormatArgs (unsigned CBSZ, unsigned BLGP, unsigned F8F8Opcode)

const GcnBufferFormatInfo *

llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)

const GcnBufferFormatInfo *

llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)

int

llvm::AMDGPU::getMCOpcode (uint16_t Opcode, unsigned Gen)

llvm::AMDGPU::getVOPDOpcode (unsigned Opc)

int

llvm::AMDGPU::getVOPDFull (unsigned OpX, unsigned OpY, unsigned EncodingFamily)

llvm::AMDGPU::isVOPD (unsigned Opc)

llvm::AMDGPU::isMAC (unsigned Opc)

llvm::AMDGPU::isPermlane16 (unsigned Opc)

llvm::AMDGPU::isGenericAtomic (unsigned Opc)

llvm::AMDGPU::isCvt_F32_Fp8_Bf8_e64 (unsigned Opc)

std::pair< unsigned, unsigned >

llvm::AMDGPU::getVOPDComponents (unsigned VOPDOpcode)

VOPD::InstInfo

llvm::AMDGPU::getVOPDInstInfo (const MCInstrDesc &OpX, const MCInstrDesc &OpY)

VOPD::InstInfo

llvm::AMDGPU::getVOPDInstInfo (unsigned VOPDOpcode, const MCInstrInfo *InstrInfo)

llvm::AMDGPU::isTrue16Inst (unsigned Opc)

FPType

llvm::AMDGPU::getFPDstSelType (unsigned Opc)

LLVM_READONLY bool

llvm::AMDGPU::isInvalidSingleUseConsumerInst (unsigned Opc)

LLVM_READONLY bool

llvm::AMDGPU::isInvalidSingleUseProducerInst (unsigned Opc)

llvm::AMDGPU::isDPMACCInstruction (unsigned Opc)

llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode (unsigned Opc)

llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode (unsigned Opc)

void

llvm::AMDGPU::initDefaultAMDKernelCodeT (AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo *STI)

llvm::AMDGPU::isGroupSegment (const GlobalValue *GV)

llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV)

llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV)

llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT)

int

llvm::AMDGPU::getIntegerAttribute (const Function &F, StringRef Name, int Default)

std::pair< unsigned, unsigned >

llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)

std::optional< std::pair< unsigned, std::optional< unsigned > > >

llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, bool OnlyFirstRequired)

SmallVector< unsigned >

llvm::AMDGPU::getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size, unsigned DefaultVal)

llvm::AMDGPU::getVmcntBitMask (const IsaVersion &Version)

llvm::AMDGPU::getExpcntBitMask (const IsaVersion &Version)

llvm::AMDGPU::getLgkmcntBitMask (const IsaVersion &Version)

llvm::AMDGPU::getWaitcntBitMask (const IsaVersion &Version)

llvm::AMDGPU::decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)

llvm::AMDGPU::decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)

llvm::AMDGPU::decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)

void

llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)

Decodes Vmcnt, Expcnt and Lgkmcnt from given [Waitcnt](structllvm%5F1%5F1AMDGPU%5F1%5F1Waitcnt.html "Represents the counter values to wait for in an s_waitcnt instruction.") for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Waitcnt

llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)

llvm::AMDGPU::encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)

llvm::AMDGPU::encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)

llvm::AMDGPU::encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)

llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)

llvm::AMDGPU::getLoadcntBitMask (const IsaVersion &Version)

llvm::AMDGPU::getSamplecntBitMask (const IsaVersion &Version)

llvm::AMDGPU::getBvhcntBitMask (const IsaVersion &Version)

llvm::AMDGPU::getDscntBitMask (const IsaVersion &Version)

llvm::AMDGPU::getKmcntBitMask (const IsaVersion &Version)

llvm::AMDGPU::getStorecntBitMask (const IsaVersion &Version)

Waitcnt

llvm::AMDGPU::decodeLoadcntDscnt (const IsaVersion &Version, unsigned LoadcntDscnt)

Waitcnt

llvm::AMDGPU::decodeStorecntDscnt (const IsaVersion &Version, unsigned StorecntDscnt)

llvm::AMDGPU::encodeLoadcntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)

llvm::AMDGPU::encodeStorecntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)

int

llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding (const MCSubtargetInfo &STI)

int

llvm::AMDGPU::DepCtr::encodeDepCtr (const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)

llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding (unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)

llvm::AMDGPU::DepCtr::decodeDepCtr (unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)

llvm::AMDGPU::DepCtr::decodeFieldVaVdst (unsigned Encoded)

llvm::AMDGPU::DepCtr::decodeFieldVmVsrc (unsigned Encoded)

llvm::AMDGPU::DepCtr::decodeFieldSaSdst (unsigned Encoded)

llvm::AMDGPU::DepCtr::encodeFieldVmVsrc (unsigned VmVsrc)

llvm::AMDGPU::DepCtr::encodeFieldVmVsrc (unsigned Encoded, unsigned VmVsrc)

llvm::AMDGPU::DepCtr::encodeFieldVaVdst (unsigned VaVdst)

llvm::AMDGPU::DepCtr::encodeFieldVaVdst (unsigned Encoded, unsigned VaVdst)

llvm::AMDGPU::DepCtr::encodeFieldSaSdst (unsigned SaSdst)

llvm::AMDGPU::DepCtr::encodeFieldSaSdst (unsigned Encoded, unsigned SaSdst)

llvm::AMDGPU::Exp::getTgtName (unsigned Id, StringRef &Name, int &Index)

llvm::AMDGPU::Exp::getTgtId (const StringRef Name)

llvm::AMDGPU::Exp::isSupportedTgtId (unsigned Id, const MCSubtargetInfo &STI)

int64_t

llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt (unsigned Dfmt, unsigned Nfmt)

void

llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt (unsigned Format, unsigned &Dfmt, unsigned &Nfmt)

int64_t

llvm::AMDGPU::MTBUFFormat::getDfmt (const StringRef Name)

StringRef

llvm::AMDGPU::MTBUFFormat::getDfmtName (unsigned Id)

int64_t

llvm::AMDGPU::MTBUFFormat::getNfmt (const StringRef Name, const MCSubtargetInfo &STI)

StringRef

llvm::AMDGPU::MTBUFFormat::getNfmtName (unsigned Id, const MCSubtargetInfo &STI)

llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt (unsigned Id, const MCSubtargetInfo &STI)

llvm::AMDGPU::MTBUFFormat::isValidNfmt (unsigned Id, const MCSubtargetInfo &STI)

int64_t

llvm::AMDGPU::MTBUFFormat::getUnifiedFormat (const StringRef Name, const MCSubtargetInfo &STI)

StringRef

llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName (unsigned Id, const MCSubtargetInfo &STI)

llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat (unsigned Id, const MCSubtargetInfo &STI)

int64_t

llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt (unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)

llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding (unsigned Val, const MCSubtargetInfo &STI)

llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding (const MCSubtargetInfo &STI)

llvm::AMDGPU::SendMsg::isValidMsgId (int64_t MsgId, const MCSubtargetInfo &STI)

llvm::AMDGPU::SendMsg::isValidMsgOp (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)

llvm::AMDGPU::SendMsg::isValidMsgStream (int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)

llvm::AMDGPU::SendMsg::msgRequiresOp (int64_t MsgId, const MCSubtargetInfo &STI)

llvm::AMDGPU::SendMsg::msgSupportsStream (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)

void

llvm::AMDGPU::SendMsg::decodeMsg (unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)

llvm::AMDGPU::SendMsg::encodeMsg (uint64_t MsgId, uint64_t OpId, uint64_t StreamId)

llvm::AMDGPU::getInitialPSInputAddr (const Function &F)

llvm::AMDGPU::getHasColorExport (const Function &F)

llvm::AMDGPU::getHasDepthExport (const Function &F)

llvm::AMDGPU::isShader (CallingConv::ID cc)

llvm::AMDGPU::isGraphics (CallingConv::ID cc)

llvm::AMDGPU::isCompute (CallingConv::ID cc)

llvm::AMDGPU::isEntryFunctionCC (CallingConv::ID CC)

llvm::AMDGPU::isModuleEntryFunctionCC (CallingConv::ID CC)

llvm::AMDGPU::isChainCC (CallingConv::ID CC)

llvm::AMDGPU::isKernelCC (const Function *Func)

LLVM_READNONE bool

llvm::AMDGPU::isKernel (CallingConv::ID CC)

llvm::AMDGPU::hasXNACK (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasSRAMECC (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasMIMG_R128 (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasA16 (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasG16 (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasPackedD16 (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasGDS (const MCSubtargetInfo &STI)

llvm::AMDGPU::getNSAMaxSize (const MCSubtargetInfo &STI, bool HasSampler)

llvm::AMDGPU::getMaxNumUserSGPRs (const MCSubtargetInfo &STI)

llvm::AMDGPU::isSI (const MCSubtargetInfo &STI)

llvm::AMDGPU::isCI (const MCSubtargetInfo &STI)

llvm::AMDGPU::isVI (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX9_GFX10 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX9_GFX10_GFX11 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX8Plus (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX9Plus (const MCSubtargetInfo &STI)

llvm::AMDGPU::isNotGFX9Plus (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX10 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX10_GFX11 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX10Plus (const MCSubtargetInfo &STI)

llvm::AMDGPU::isNotGFX10Plus (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX10Before1030 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX11 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX11Plus (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX12 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX12Plus (const MCSubtargetInfo &STI)

llvm::AMDGPU::isNotGFX12Plus (const MCSubtargetInfo &STI)

llvm::AMDGPU::isNotGFX11Plus (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGCN3Encoding (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX10_AEncoding (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX10_BEncoding (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasGFX10_3Insts (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX10_3_GFX11 (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX90A (const MCSubtargetInfo &STI)

llvm::AMDGPU::isGFX940 (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasArchitectedFlatScratch (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasMAIInsts (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasVOPD (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasDPPSrc1SGPR (const MCSubtargetInfo &STI)

int32_t

llvm::AMDGPU::getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)

llvm::AMDGPU::hasKernargPreload (const MCSubtargetInfo &STI)

llvm::AMDGPU::hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)

llvm::AMDGPU::isSGPR (MCRegister Reg, const MCRegisterInfo *TRI)

Is Reg - scalar register.

llvm::AMDGPU::isHi16Reg (MCRegister Reg, const MCRegisterInfo &MRI)

MCRegister

llvm::AMDGPU::getMCReg (MCRegister Reg, const MCSubtargetInfo &STI)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

MCRegister

llvm::AMDGPU::mc2PseudoReg (MCRegister Reg)

Convert hardware register Reg to a pseudo register.

llvm::AMDGPU::isInlineValue (unsigned Reg)

llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)

Is this an AMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).

llvm::AMDGPU::isKImmOperand (const MCInstrDesc &Desc, unsigned OpNo)

Is this a KImm operand?

llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)

Is this floating-point operand?

llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)

Does this operand support only inlinable literals?

llvm::AMDGPU::getRegBitWidth (unsigned RCID)

Get the size in bits of a register from the register class RC.

llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC)

Get the size in bits of a register from the register class RC.

llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)

Get size of register operand.

LLVM_READNONE unsigned

llvm::AMDGPU::getOperandSize (const MCOperandInfo &OpInfo)

LLVM_READNONE unsigned

llvm::AMDGPU::getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)

LLVM_READNONE bool

llvm::AMDGPU::isInlinableIntLiteral (int64_t Literal)

Is this literal inlinable, and not one of the values intended for floating point values.

llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)

Is this literal inlinable.

llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)

llvm::AMDGPU::isInlinableLiteralBF16 (int16_t Literal, bool HasInv2Pi)

llvm::AMDGPU::isInlinableLiteralFP16 (int16_t Literal, bool HasInv2Pi)

llvm::AMDGPU::isInlinableLiteralI16 (int32_t Literal, bool HasInv2Pi)

std::optional< unsigned >

llvm::AMDGPU::getInlineEncodingV2I16 (uint32_t Literal)

std::optional< unsigned >

llvm::AMDGPU::getInlineEncodingV2BF16 (uint32_t Literal)

std::optional< unsigned >

llvm::AMDGPU::getInlineEncodingV2F16 (uint32_t Literal)

llvm::AMDGPU::isInlinableLiteralV216 (uint32_t Literal, uint8_t OpType)

llvm::AMDGPU::isInlinableLiteralV2I16 (uint32_t Literal)

llvm::AMDGPU::isInlinableLiteralV2BF16 (uint32_t Literal)

llvm::AMDGPU::isInlinableLiteralV2F16 (uint32_t Literal)

llvm::AMDGPU::isValid32BitLiteral (uint64_t Val, bool IsFP64)

llvm::AMDGPU::isArgPassedInSGPR (const Argument *A)

llvm::AMDGPU::isArgPassedInSGPR (const CallBase *CB, unsigned ArgNo)

llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)

llvm::AMDGPU::isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)

llvm::AMDGPU::convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)

Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.

std::optional< int64_t >

llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)

std::optional< int64_t >

llvm::AMDGPU::getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)

llvm::AMDGPU::getNumFlatOffsetBits (const MCSubtargetInfo &ST)

For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.

llvm::AMDGPU::isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)

LLVM_READNONE bool

llvm::AMDGPU::isLegalDPALU_DPPControl (unsigned DC)

llvm::AMDGPU::hasAny64BitVGPROperands (const MCInstrDesc &OpDesc)

llvm::AMDGPU::isDPALU_DPP (const MCInstrDesc &OpDesc)

llvm::AMDGPU::isIntrinsicSourceOfDivergence (unsigned IntrID)

llvm::AMDGPU::isIntrinsicAlwaysUniform (unsigned IntrID)

llvm::AMDGPU::getLdsDwGranularity (const MCSubtargetInfo &ST)

raw_ostream &

llvm::operator<< (raw_ostream &OS, const AMDGPU::IsaInfo::TargetIDSetting S)