LLVM: lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h Source File (original) (raw)

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17#ifndef LLVM_LIB_TARGET_AMDGPU_MCA_AMDGPUCUSTOMBEHAVIOUR_H

18#define LLVM_LIB_TARGET_AMDGPU_MCA_AMDGPUCUSTOMBEHAVIOUR_H

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25namespace llvm {

26namespace mca {

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57 std::vector InstrWaitCntInfo;

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66 void generateWaitCntInfo();

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68 bool hasModifiersSet(const std::unique_ptr &Inst,

69 AMDGPU::OpName OpName) const;

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71 bool isGWS(uint16_t Opcode) const;

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73 bool isAlwaysGDS(uint16_t Opcode) const;

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84 void computeWaitCnt(const InstRef &IR, unsigned &Vmcnt, unsigned &Expcnt,

85 unsigned &Lgkmcnt, unsigned &Vscnt);

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87public:

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101};

102}

103}

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105#endif

This file defines the base class CustomBehaviour which can be inherited from by specific targets (ex.

Legalize the Machine IR a function s Machine IR

This file defines the SmallVector class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

Interface to description of machine instruction set.

Generic base class for all target subtargets.

unsigned checkCustomHazard(ArrayRef< InstRef > IssuedInst, const InstRef &IR) override

This method is used to determine if an instruction should be allowed to be dispatched.

~AMDGPUCustomBehaviour() override=default

AMDGPUCustomBehaviour(const MCSubtargetInfo &STI, const mca::SourceMgr &SrcMgr, const MCInstrInfo &MCII)

void postProcessInstruction(Instruction &Inst, const MCInst &MCI) override

This method can be overriden by targets to modify the mca::Instruction object after it has been lower...

AMDGPUInstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)

Definition AMDGPUCustomBehaviour.h:32

~AMDGPUInstrPostProcess() override=default

const mca::SourceMgr & SrcMgr

const MCSubtargetInfo & STI

CustomBehaviour(const MCSubtargetInfo &STI, const mca::SourceMgr &SrcMgr, const MCInstrInfo &MCII)

An InstRef contains both a SourceMgr index and Instruction pair.

const MCSubtargetInfo & STI

InstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)

An instruction propagated through the simulated instruction pipeline.

This is an optimization pass for GlobalISel generic memory operations.

Abstracting the input code sequence (a sequence of MCInst) and assigning unique identifiers to every ...

bool LgkmCnt

Definition AMDGPUCustomBehaviour.h:43

bool ExpCnt

Definition AMDGPUCustomBehaviour.h:42

bool VsCnt

Definition AMDGPUCustomBehaviour.h:44

bool VmCnt

Definition AMDGPUCustomBehaviour.h:41