AMDGPUExportClustering.cpp Source File (original) (raw)

18using namespace llvm;

20namespace {

23public:

24 ExportClustering() = default;

25 void apply(ScheduleDAGInstrs *DAG) override;

26};

28static bool isExport(const SUnit &SU) {

30}

34 unsigned Imm = TII->getNamedOperand(*MI, AMDGPU::OpName::tgt)->getImm();

36}

39 unsigned PosCount) {

40 if (!PosCount || PosCount == Chain.size())

41 return;

48 unsigned PosIdx = 0;

49 unsigned OtherIdx = PosCount;

50 for (SUnit *SU : Copy) {

51 if (isPositionExport(TII, SU))

52 Chain[PosIdx++] = SU;

53 else

54 Chain[OtherIdx++] = SU;

55 }

56}

62 for (unsigned Idx = 0, End = Exports.size() - 1; Idx < End; ++Idx) {

63 SUnit *SUa = Exports[Idx];

64 SUnit *SUb = Exports[Idx + 1];

68 for (const SDep &Pred : SUb->Preds) {

69 SUnit *PredSU = Pred.getSUnit();

70 if (!isExport(*PredSU) && !Pred.isWeak())

72 }

78 }

79}

84 for (const SDep &Pred : SU.Preds) {

85 SUnit *PredSU = Pred.getSUnit();

86 if (Pred.isBarrier() && isExport(*PredSU)) {

88 if (isExport(SU))

89 continue;

93 for (const SDep &ExportPred : PredSU->Preds) {

95 if (ExportPred.isBarrier() && !isExport(*ExportPredSU))

97 }

98 }

99 }

100

103 for (SDep Pred : ToAdd)

105}

106

108 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(DAG->TII);

109

111

112

113

114

115

116 unsigned PosCount = 0;

117 for (SUnit &SU : DAG->SUnits) {

118 if (!isExport(SU))

119 continue;

120

122 if (isPositionExport(TII, &SU))

123 PosCount++;

124

125 removeExportDependencies(DAG, SU);

126

128 for (SDep Succ : Succs)

129 removeExportDependencies(DAG, *Succ.getSUnit());

130 }

131

132

133 if (Chain.size() > 1) {

134 sortChain(TII, Chain, PosCount);

135 buildCluster(Chain, DAG);

136 }

137}

138

139}

140

141std::unique_ptr

143 return std::make_unique();

144}

const TargetInstrInfo & TII

ReachingDefInfo InstSet & ToRemove

Interface definition for SIInstrInfo.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

const T & front() const

front - Get the first element.

size_t size() const

size - Get the array size.

Representation of each machine instruction.

@ Cluster

Weak DAG edge linking a chain of clustered instrs.

@ Barrier

An unknown scheduling barrier.

@ Artificial

Arbitrary strong DAG edge (no real dependence).

bool isBarrier() const

Tests if this is an Order dependence that is marked as a barrier.

static bool isEXP(const MachineInstr &MI)

Scheduling unit. This is a node in the scheduling DAG.

LLVM_ABI void removePred(const SDep &D)

Removes the specified edge as a pred of the current node if it exists.

SmallVector< SDep, 4 > Succs

All sunit successors.

SmallVector< SDep, 4 > Preds

All sunit predecessors.

MachineInstr * getInstr() const

Returns the representative MachineInstr for this SUnit.

A ScheduleDAG for scheduling lists of MachineInstr.

bool addEdge(SUnit *SuccSU, const SDep &PredDep)

Add a DAG edge to the given SU with the given predecessor dependence data.

Mutate the DAG as a postpass after normal DAG building.

const TargetInstrInfo * TII

Target instruction information.

std::vector< SUnit > SUnits

The scheduling units.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

void apply(Opt *O, const Mod &M, const Mods &... Ms)

This is an optimization pass for GlobalISel generic memory operations.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

std::unique_ptr< ScheduleDAGMutation > createAMDGPUExportClusteringDAGMutation()

Definition AMDGPUExportClustering.cpp:142