AMDGPUInstructionSelector.h Source File (original) (raw)

49private:

53public:

65private:

66 struct GEPInfo {

69 int64_t Imm = 0;

70 };

86 unsigned SubIdx) const;

88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;

101 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;

102 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;

105 bool selectG_MERGE_VALUES(MachineInstr &I) const;

106 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;

107 bool selectG_BUILD_VECTOR(MachineInstr &I) const;

108 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;

111

118 bool selectGroupStaticSize(MachineInstr &I) const;

121

125 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;

127 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;

128

131 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;

133 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;

137

139 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;

142 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;

144 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;

145 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;

148 bool selectBVHIntersectRayIntrinsic(MachineInstr &I) const;

159

160 std::pair<Register, unsigned> selectVOP3ModsImpl(Register Src,

161 bool IsCanonicalizing = true,

162 bool AllowAbs = true,

163 bool OpSel = false) const;

164

167 bool ForceVGPR = false) const;

168

171

174

184 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;

187

189

190 std::pair<Register, unsigned>

192 bool IsDOT = false) const;

194 selectVOP3PRetHelper(MachineOperand &Root, bool IsDOT = false) const;

195

198

201

203 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;

204

219

222

227

229 bool IsSigned) const;

231 int64_t *Offset, bool *ScaleOffset) const;

240

241 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,

243

250

252 selectGlobalSAddr(MachineOperand &Root, unsigned CPolBits,

253 bool NeedIOffset = true) const;

263 selectGlobalSAddrNoIOffset(MachineOperand &Root) const;

265 selectGlobalSAddrNoIOffsetM0(MachineOperand &Root) const;

266

269 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,

273

277 selectMUBUFScratchOffset(MachineOperand &Root) const;

278

280 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,

281 unsigned Size) const;

282 bool isFlatScratchBaseLegal(Register Addr) const;

283 bool isFlatScratchBaseLegalSV(Register Addr) const;

284 bool isFlatScratchBaseLegalSVImm(Register Addr) const;

285

286 std::pair<Register, unsigned>

287 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;

290

292 selectDS64Bit4ByteAligned(MachineOperand &Root) const;

293

295 selectDS128Bit8ByteAligned(MachineOperand &Root) const;

296

297 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,

298 unsigned size) const;

301

302 std::tuple<Register, int64_t, bool>

303 getPtrBaseWithConstantOffset(Register Root,

305

306

307

308

309 struct MUBUFAddressData {

312 };

313

314 bool shouldUseAddr64(MUBUFAddressData AddrData) const;

315

316 void splitIllegalMUBUFOffset(MachineIRBuilder &B,

317 Register &SOffset, int64_t &ImmOffset) const;

318

319 MUBUFAddressData parseMUBUFAddress(Register Src) const;

320

321 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,

323 int64_t &Offset) const;

324

325 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,

327

329 selectBUFSOffset(MachineOperand &Root) const;

330

332 selectMUBUFAddr64(MachineOperand &Root) const;

333

335 selectMUBUFOffset(MachineOperand &Root) const;

336

338 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;

339 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;

340

341 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,

342 bool &Matched) const;

343 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;

344 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;

345

346 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,

347 int OpIdx = -1) const;

348

349 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,

350 int OpIdx) const;

351 void renderZextBoolTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,

352 int OpIdx) const;

353

354 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,

355 int OpIdx) const;

356

357 void renderSrcAndDstSelToOpSelXForm_0_0(MachineInstrBuilder &MIB,

358 const MachineInstr &MI,

359 int OpIdx) const;

360

361 void renderSrcAndDstSelToOpSelXForm_0_1(MachineInstrBuilder &MIB,

362 const MachineInstr &MI,

363 int OpIdx) const;

364

365 void renderSrcAndDstSelToOpSelXForm_1_0(MachineInstrBuilder &MIB,

366 const MachineInstr &MI,

367 int OpIdx) const;

368

369 void renderSrcAndDstSelToOpSelXForm_1_1(MachineInstrBuilder &MIB,

370 const MachineInstr &MI,

371 int OpIdx) const;

372

373 void renderDstSelToOpSelXForm(MachineInstrBuilder &MIB,

374 const MachineInstr &MI, int OpIdx) const;

375

376 void renderSrcSelToOpSelXForm(MachineInstrBuilder &MIB,

377 const MachineInstr &MI, int OpIdx) const;

378

379 void renderSrcAndDstSelToOpSelXForm_2_0(MachineInstrBuilder &MIB,

380 const MachineInstr &MI,

381 int OpIdx) const;

382

383 void renderDstSelToOpSel3XFormXForm(MachineInstrBuilder &MIB,

384 const MachineInstr &MI, int OpIdx) const;

385

386 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,

387 int OpIdx) const;

388

389 void renderBitcastFPImm(MachineInstrBuilder &MIB, const MachineInstr &MI,

390 int OpIdx) const;

391

392 void renderBitcastFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,

393 int OpIdx) const {

394 renderBitcastFPImm(MIB, MI, OpIdx);

395 }

396 void renderBitcastFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,

397 int OpIdx) const {

398 renderBitcastFPImm(MIB, MI, OpIdx);

399 }

400

401 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,

402 int OpIdx) const;

403 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,

404 int OpIdx) const;

405 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,

406 int OpIdx) const;

407 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,

408 int OpIdx) const;

409

410 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,

411 int OpIdx) const;

412

413 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,

414 int OpIdx) const;

415

416 void renderRoundMode(MachineInstrBuilder &MIB, const MachineInstr &MI,

417 int OpIdx) const;

418

419 void renderVOP3PModsNeg(MachineInstrBuilder &MIB, const MachineInstr &MI,

420 int OpIdx) const;

421 void renderVOP3PModsNegs(MachineInstrBuilder &MIB, const MachineInstr &MI,

422 int OpIdx) const;

423 void renderVOP3PModsNegAbs(MachineInstrBuilder &MIB, const MachineInstr &MI,

424 int OpIdx) const;

425

426 void renderPrefetchLoc(MachineInstrBuilder &MIB, const MachineInstr &MI,

427 int OpIdx) const;

428

429 void renderScaledMAIIntrinsicOperand(MachineInstrBuilder &MIB,

430 const MachineInstr &MI, int OpIdx) const;

431

432 bool isInlineImmediate(const APInt &Imm) const;

433 bool isInlineImmediate(const APFloat &Imm) const;

434

435

436

437 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;

438

439

441

443

444

446

447

449

450

452

454

455 const SIInstrInfo &TII;

456 const SIRegisterInfo &TRI;

457 const AMDGPURegisterBankInfo &RBI;

458 const AMDGPUTargetMachine &TM;

459 const GCNSubtarget &STI;

460#define GET_GLOBALISEL_PREDICATES_DECL

461#define AMDGPUSubtarget GCNSubtarget

462#include "AMDGPUGenGlobalISel.inc"

463#undef GET_GLOBALISEL_PREDICATES_DECL

464#undef AMDGPUSubtarget

465

466#define GET_GLOBALISEL_TEMPORARIES_DECL

467#include "AMDGPUGenGlobalISel.inc"

468#undef GET_GLOBALISEL_TEMPORARIES_DECL

469};