AMDGPUMCKernelDescriptor.cpp Source File (original) (raw)

17using namespace llvm;

41 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,

42 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Ctx);

46 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,

47 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP, Ctx);

50 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,

51 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE, Ctx);

52 }

55 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,

56 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Ctx);

57 if (Version.Major >= 10) {

61 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,

62 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, Ctx);

66 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,

67 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE, Ctx);

71 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,

72 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED, Ctx);

76 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS_SHIFT,

77 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS, Ctx);

78 }

82 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,

83 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Ctx);

84 return KD;

85}

AMDHSA kernel descriptor MCExpr struct for use in MC layer.

Provides AMDGPU specific target descriptions.

constexpr bool test(unsigned I) const

static const MCBinaryExpr * createLShr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

static const MCBinaryExpr * createAnd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

static const MCBinaryExpr * createOr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

static const MCBinaryExpr * createShl(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

Base class for the full range of assembler expressions which are needed for parsing.

Generic base class for all target subtargets.

const FeatureBitset & getFeatureBits() const

static const MCUnaryExpr * createNot(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())

LLVM Value Representation.

LLVM_ABI IsaVersion getIsaVersion(StringRef GPU)

bool isGFX90A(const MCSubtargetInfo &STI)

@ FLOAT_DENORM_MODE_FLUSH_NONE

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr uintptr_t uintptr_t Version

Instruction set architecture version.

const MCExpr * compute_pgm_rsrc2

const MCExpr * kernarg_size

const MCExpr * kernarg_preload

const MCExpr * compute_pgm_rsrc3

const MCExpr * private_segment_fixed_size

static const MCExpr * bits_get(const MCExpr *Src, uint32_t Shift, uint32_t Mask, MCContext &Ctx)

Definition AMDGPUMCKernelDescriptor.cpp:97

const MCExpr * compute_pgm_rsrc1

static void bits_set(const MCExpr *&Dst, const MCExpr *Value, uint32_t Shift, uint32_t Mask, MCContext &Ctx)

Definition AMDGPUMCKernelDescriptor.cpp:87

const MCExpr * group_segment_fixed_size

static MCKernelDescriptor getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI, MCContext &Ctx)

Definition AMDGPUMCKernelDescriptor.cpp:21

const MCExpr * kernel_code_properties