AMDGPURegisterBankInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H

14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H

21#define GET_REGBANK_DECLARATIONS

22#include "AMDGPUGenRegisterBank.inc"

24namespace llvm {

26class LLT;

27class GCNSubtarget;

28class MachineIRBuilder;

29class SIInstrInfo;

30class SIRegisterInfo;

31class TargetRegisterInfo;

36protected:

38#define GET_TARGET_REGBANK_CLASS

39#include "AMDGPUGenRegisterBank.inc"

40};

43public:

67 unsigned OpIdx) const;

77 int64_t &InstOffsetVal, Align Alignment) const;

93 std::pair<Register, unsigned>

102

105

107 unsigned Default = AMDGPU::VGPRRegBankID) const;

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128 LLT HalfTy,

130

131 template

136

137 template

140 const std::array<unsigned, NumOps> RegSrcOpIdx,

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163 int RsrcIdx) const;

164

165public:

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174 const RegisterBank *CurBank = nullptr) const override;

175

177 LLT) const override;

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186

187private:

192};

193}

194#endif

unsigned const MachineRegisterInfo * MRI

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

MachineInstr unsigned OpIdx

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

This file defines the SmallSet class.

This class provides the information for the target register banks.

Definition AMDGPURegisterBankInfo.h:34

bool applyMappingDynStackAlloc(MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const

std::pair< Register, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register Offset) const

bool collectWaterfallOperands(SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const

const InstructionMapping & getImageMapping(const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const

InstructionMappings addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps > > Table) const

unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsicWSideEffects(const MachineInstr &MI, const MachineRegisterInfo &MRI) const

bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const

bool executeInWaterfallLoop(MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs) const

Legalize instruction MI where operands in OpIndices must be SGPRs.

const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override

Get a register bank that covers RC.

AMDGPURegisterBankInfo(const GCNSubtarget &STI)

bool applyMappingMAD_64_32(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const

unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, unsigned Default=AMDGPU::VGPRRegBankID) const

Handle register layout difference for f16 images for some subtargets.

const RegisterBankInfo::InstructionMapping & getInstrMappingForLoad(const MachineInstr &MI) const

void applyMappingImpl(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const override

See RegisterBankInfo::applyMapping.

bool applyMappingBFE(MachineIRBuilder &B, const OperandsMapper &OpdMapper, bool Signed) const

bool applyMappingImage(MachineIRBuilder &B, MachineInstr &MI, const OperandsMapper &OpdMapper, int RSrcIdx) const

const ValueMapping * getVGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const

const SIInstrInfo * TII

Definition AMDGPURegisterBankInfo.h:46

bool isScalarLoadLegal(const MachineInstr &MI) const

unsigned setBufferOffsets(MachineIRBuilder &B, Register CombinedOffset, Register &VOffsetReg, Register &SOffsetReg, int64_t &InstOffsetVal, Align Alignment) const

const ValueMapping * getSGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const

bool applyMappingLoad(MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const

void split64BitValueForMapping(MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) const

Split 64-bit value Reg into two 32-bit halves and populate them into Regs.

const ValueMapping * getValueMappingForPtr(const MachineRegisterInfo &MRI, Register Ptr) const

Return the mapping for a pointer argument.

unsigned getMappingType(const MachineRegisterInfo &MRI, const MachineInstr &MI) const

RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsic(const MachineInstr &MI, const MachineRegisterInfo &MRI) const

bool isDivergentRegBank(const RegisterBank *RB) const override

Returns true if the register bank is considered divergent.

void constrainOpWithReadfirstlane(MachineIRBuilder &B, MachineInstr &MI, unsigned OpIdx) const

InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override

Get the alternative mappings for MI.

const InstructionMapping & getDefaultMappingSOP(const MachineInstr &MI) const

const InstructionMapping & getDefaultMappingAllVGPR(const MachineInstr &MI) const

const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override

This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMapping...

unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const override

Get the cost of using ValMapping to decompose a register.

const ValueMapping * getAGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const

const GCNSubtarget & Subtarget

Definition AMDGPURegisterBankInfo.h:44

const InstructionMapping & getDefaultMappingVOP(const MachineInstr &MI) const

bool isSALUMapping(const MachineInstr &MI) const

bool applyMappingSBufferLoad(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const

void applyMappingSMULU64(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const

const SIRegisterInfo * TRI

Definition AMDGPURegisterBankInfo.h:45

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Helper class to build MachineInstr.

Representation of each machine instruction.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Helper class that represents how the value of an instruction may be mapped and what is the related co...

Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...

RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode)

Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.

SmallVector< const InstructionMapping *, 4 > InstructionMappings

Convenient type to represent the alternatives for mapping an instruction.

This class implements the register bank concept.

Wrapper class representing virtual and physical registers.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

A range adaptor for a pair of iterators.

This is an optimization pass for GlobalISel generic memory operations.

@ Default

The result values are uniform if and only if all operands are uniform.

Definition AMDGPURegisterBankInfo.h:132

int8_t RegBanks[NumOps]

Definition AMDGPURegisterBankInfo.h:133

int16_t Cost

Definition AMDGPURegisterBankInfo.h:134

This struct is a compact representation of a valid (non-zero power of two) alignment.

Helper struct that represents how a value is mapped through different register banks.