ARCDisassembler.cpp Source File (original) (raw)

27using namespace llvm;

30#define DEBUG_TYPE "arc-disassembler"

34namespace {

38public:

39 std::unique_ptr const MCII;

48};

50}

56 Insn =

57 (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);

58 return true;

59}

64 Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |

68 return true;

69}

74 Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |

77 return true;

78}

83 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);

84 return true;

85}

87template

92template

97template

101

104

107

110

113

116

119

122

125

127 ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,

128 ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,

129 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,

130 ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,

131 ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK};

132

136 if (RegNo >= 32) {

139 }

140

144}

145

149

150 if (RegNo > 3)

151 RegNo += 8;

152

154}

155

156#include "ARCGenDisassemblerTables.inc"

157

161

166

170

173

174 unsigned S9 = Insn & 0x1ff;

175 unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;

179}

180

184 static const uint64_t AtLeast = 2;

186 Inst, Value, Address, true, 0, AtLeast, 0));

187}

188

197

198template

202

203 static_assert(B > 0, "field is empty");

206}

207

208template

212

213 static_assert(B > 0, "field is empty");

217}

218

219template

223

224 static_assert(B > 0, "field is empty");

225 const unsigned max = (1u << B) - 1;

229}

230

234 unsigned SrcC, DstB, LImm;

236 if (DstB != 62) {

237 LLVM_DEBUG(dbgs() << "Decoding StLImm found non-limm register.");

239 }

242 LImm = (Insn >> 32);

246}

247

251 unsigned DstA, SrcB, LImm;

254 if (SrcB != 62) {

255 LLVM_DEBUG(dbgs() << "Decoding LdLImm found non-limm register.");

257 }

260 LImm = (Insn >> 32);

264}

265

269 unsigned DstA, SrcB;

276 LLVM_DEBUG(dbgs() << "Decoding LdRLimm found non-limm register.");

278 }

281}

282

287 using Field = decltype(Insn);

292

293 auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum,

295 if (30 == RegNum) {

298 }

299

301 };

302

305

306 return DecodeRegisterOrImm(H, Insn >> 16u);

307}

308

312 unsigned DstB;

313 LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n");

316 using Field = decltype(Insn);

322}

323

329 using Field = decltype(Insn);

333}

334

340 using Field = decltype(Insn);

347}

348

354 if (Bytes.size() < 2) {

357 }

358 uint8_t DecodeByte = (Bytes[1] & 0xF7) >> 3;

359

360

361 if (DecodeByte < 0x08) {

362

363 if (Bytes.size() < 4) {

364

367 }

368 if (Bytes.size() >= 8) {

369

370 uint64_t Insn64;

374 decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI);

376 LLVM_DEBUG(dbgs() << "Successfully decoded 64-bit instruction.");

378 }

379 LLVM_DEBUG(dbgs() << "Not a 64-bit instruction, falling back to 32-bit.");

380 }

381 uint32_t Insn32;

384 }

385

386 return decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI);

387 } else {

388 if (Bytes.size() >= 6) {

389

390 uint64_t Insn48;

394 decodeInstruction(DecoderTable48, Instr, Insn48, Address, this, STI);

397 dbgs() << "Successfully decoded 16-bit instruction with limm.");

399 }

401 dbgs() << "Not a 16-bit instruction with limm, try without it.");

402 }

403

404 uint32_t Insn16;

407

408

409 return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI);

410 }

411}

412

416 return new ARCDisassembler(STI, Ctx, T.createMCInstrInfo());

417}

418

MCDisassembler::DecodeStatus DecodeStatus

static DecodeStatus DecodeCCRU6Instruction(MCInst &, uint64_t, uint64_t, const MCDisassembler *)

Definition ARCDisassembler.cpp:309

static bool readInstruction48(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn)

Definition ARCDisassembler.cpp:71

static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t, const MCDisassembler *)

Definition ARCDisassembler.cpp:266

static DecodeStatus DecodeSOPwithRU6(MCInst &, uint64_t, uint64_t, const MCDisassembler *)

Definition ARCDisassembler.cpp:324

static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t, uint64_t, const MCDisassembler *)

Definition ARCDisassembler.cpp:283

static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS, uint64_t Address, const MCDisassembler *Decoder)

Definition ARCDisassembler.cpp:199

static unsigned decodeCField(unsigned Insn)

Definition ARCDisassembler.cpp:158

static bool readInstruction64(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn)

Definition ARCDisassembler.cpp:61

static unsigned decodeBField(unsigned Insn)

Definition ARCDisassembler.cpp:162

static MCDisassembler * createARCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition ARCDisassembler.cpp:413

static DecodeStatus DecodeSOPwithRS12(MCInst &, uint64_t, uint64_t, const MCDisassembler *)

Definition ARCDisassembler.cpp:335

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCDisassembler()

Definition ARCDisassembler.cpp:419

static bool readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

Definition ARCDisassembler.cpp:80

static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

Definition ARCDisassembler.cpp:52

static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARCDisassembler.cpp:133

static DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t, const MCDisassembler *)

Definition ARCDisassembler.cpp:248

static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, uint64_t Address=0, const MCDisassembler *Decoder=nullptr)

Definition ARCDisassembler.cpp:220

static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS, uint64_t Address=0, const MCDisassembler *Decoder=nullptr)

Definition ARCDisassembler.cpp:209

static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition ARCDisassembler.cpp:146

static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t, const MCDisassembler *)

Definition ARCDisassembler.cpp:231

static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address, uint64_t Offset, const MCDisassembler *Decoder)

Definition ARCDisassembler.cpp:189

static const uint16_t GPR32DecoderTable[]

Definition ARCDisassembler.cpp:126

static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t, const MCDisassembler *)

Definition ARCDisassembler.cpp:171

static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address, uint64_t Value, const MCDisassembler *Decoder)

Definition ARCDisassembler.cpp:181

static unsigned decodeAField(unsigned Insn)

Definition ARCDisassembler.cpp:167

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

#define LLVM_EXTERNAL_VISIBILITY

OptimizedStructLayoutField Field

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Context object for machine code objects.

Superclass for all disassemblers.

bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

Interface to description of machine instruction set.

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

Generic base class for all target subtargets.

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)

This is an optimization pass for GlobalISel generic memory operations.

GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)

Target & getTheARCTarget()

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr int32_t SignExtend32(uint32_t X)

Sign-extend the number in the bottom B bits of X to a 32-bit integer.

constexpr T maskTrailingOnes(unsigned N)

Create a bitmask with the N right-most bits set to 1, and all other bits set to 0.

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.