ARCInstrInfo.cpp Source File (original) (raw)

24using namespace llvm;

26#define GET_INSTRINFO_CTOR_DTOR

27#include "ARCGenInstrInfo.inc"

29#define DEBUG_TYPE "arc-inst-info"

44void ARCInstrInfo::anchor() {}

47 : ARCGenInstrInfo(ST, RI, ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP),

48 RI(ST) {}

51 return Op.isImm() && Op.getImm() == 0;

52}

54static bool isLoad(int Opcode) {

55 return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 ||

56 Opcode == ARC::LDB_rs9;

57}

60 return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 ||

61 Opcode == ARC::STB_rs9;

62}

70 int &FrameIndex) const {

71 int Opcode = MI.getOpcode();

73 if ((MI.getOperand(1).isFI()) &&

74 (MI.getOperand(2).isImm()) &&

76 FrameIndex = MI.getOperand(1).getIndex();

77 return MI.getOperand(0).getReg();

78 }

79 }

80 return 0;

81}

89 int &FrameIndex) const {

90 int Opcode = MI.getOpcode();

92 if ((MI.getOperand(1).isFI()) &&

93 (MI.getOperand(2).isImm()) &&

95 FrameIndex = MI.getOperand(1).getIndex();

96 return MI.getOperand(0).getReg();

97 }

98 }

99 return 0;

100}

101

102

104 switch (CC) {

105 default:

135 }

136}

137

139

141 return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p;

142}

143

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170

175 bool AllowModify) const {

176 TBB = FBB = nullptr;

178 if (I == MBB.begin())

179 return false;

180 --I;

181

182 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {

183

184

185

186 bool CantAnalyze = false;

187

188

189 while (I->isDebugInstr() || ->isTerminator()) {

190 if (I == MBB.begin())

191 return false;

192 --I;

193 }

194

196

197

198 CantAnalyze = true;

200 TBB = I->getOperand(0).getMBB();

202

203 if ( Cond .empty())

204 return true;

205

206 assert(!FBB && "FBB should have been null.");

207 FBB = TBB;

208 TBB = I->getOperand(0).getMBB();

209 Cond.push_back(I->getOperand(1));

210 Cond.push_back(I->getOperand(2));

211 Cond.push_back(I->getOperand(3));

212 } else if (I->isReturn()) {

213

214 CantAnalyze = !isPredicated(*I);

215 } else {

216

217 return true;

218 }

219

220

221

224

225

226 Cond.clear();

227 FBB = nullptr;

228

229

230

231 if (AllowModify) {

233 while (DI != MBB.end()) {

235 ++DI;

237 }

238 }

239 }

240

241 if (CantAnalyze)

242 return true;

243

244 if (I == MBB.begin())

245 return false;

246

247 --I;

248 }

249

250

251

252 return false;

253}

254

256 int *BytesRemoved) const {

257 assert(!BytesRemoved && "Code size not handled");

259 if (I == MBB.end())

260 return 0;

261

264 return 0;

265

266

267 I->eraseFromParent();

268

269 I = MBB.end();

270

271 if (I == MBB.begin())

272 return 1;

273 --I;

275 return 1;

276

277

278 I->eraseFromParent();

279 return 2;

280}

281

285 Register SrcReg, bool KillSrc,

286 bool RenamableDest, bool RenamableSrc) const {

288 "Only GPR32 src copy supported.");

290 "Only GPR32 dest copy supported.");

293}

294

302

307

308 assert(MMO && "Couldn't get MachineMemOperand for store to stack.");

309 assert(TRI.getSpillSize(*RC) == 4 &&

310 "Only support 4-byte stores to stack now.");

311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&

312 "Only support GPR32 stores to stack now.");

314 << " to FrameIndex=" << FrameIndex << "\n");

320}

321

324 Register DestReg, int FrameIndex,

335

336 assert(MMO && "Couldn't get MachineMemOperand for store to stack.");

337 assert(TRI.getSpillSize(*RC) == 4 &&

338 "Only support 4-byte loads from stack now.");

339 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&

340 "Only support GPR32 stores to stack now.");

342 << " from FrameIndex=" << FrameIndex << "\n");

348}

349

350

353 assert((Cond.size() == 3) && "Invalid ARC branch condition!");

355 return false;

356}

357

370

375 const DebugLoc &DL, int *BytesAdded) const {

376 assert(!BytesAdded && "Code size not handled.");

377

378

379 assert(TBB && "insertBranch must not be told to insert a fallthrough");

381 "ARC branch conditions have two components!");

382

383 if (Cond.empty()) {

385 return 1;

386 }

387 int BccOpc = Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p;

390 for (unsigned i = 0; i < 3; i++) {

392 }

393

394

395 if (!FBB) {

396 return 1;

397 }

398

399

401 return 2;

402}

403

405 if (MI.isInlineAsm()) {

407 const char *AsmStr = MI.getOperand(0).getSymbolName();

409 }

410 return MI.getDesc().getSize();

411}

412

418

424

426 unsigned &BasePos,

427 unsigned &OffsetPos) const {

428 if (.mayLoad() && .mayStore())

429 return false;

430

431 BasePos = 1;

432 OffsetPos = 2;

433

435 BasePos++;

436 OffsetPos++;

437 }

438

439 if (.getOperand(BasePos).isReg() || .getOperand(OffsetPos).isImm())

440 return false;

441

442 return true;

443}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

TSFlagsConstants

Definition ARCInstrInfo.cpp:38

@ TSF_AddModeMask

Definition ARCInstrInfo.cpp:40

@ TSF_AddrModeOff

Definition ARCInstrInfo.cpp:39

AddrIncType

Definition ARCInstrInfo.cpp:31

@ PostInc

Definition ARCInstrInfo.cpp:34

@ PreInc

Definition ARCInstrInfo.cpp:33

@ Scaled

Definition ARCInstrInfo.cpp:35

@ NoAddInc

Definition ARCInstrInfo.cpp:32

static bool isLoad(int Opcode)

Definition ARCInstrInfo.cpp:54

static ARCCC::CondCode getOppositeBranchCondition(ARCCC::CondCode CC)

Return the inverse of passed condition, i.e. turning COND_E to COND_NE.

Definition ARCInstrInfo.cpp:103

static bool isStore(int Opcode)

Definition ARCInstrInfo.cpp:59

static bool isZeroImm(const MachineOperand &Op)

Definition ARCInstrInfo.cpp:50

static bool isJumpOpcode(int Opc)

Definition ARCInstrInfo.cpp:144

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &, int *BytesAdded=nullptr) const override

Definition ARCInstrInfo.cpp:371

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition ARCInstrInfo.cpp:282

virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override

Definition ARCInstrInfo.cpp:425

bool isPostIncrement(const MachineInstr &MI) const override

Definition ARCInstrInfo.cpp:413

If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...

Definition ARCInstrInfo.cpp:88

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition ARCInstrInfo.cpp:295

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....

Definition ARCInstrInfo.cpp:171

MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const

Definition ARCInstrInfo.cpp:359

ARCInstrInfo(const ARCSubtarget &)

Definition ARCInstrInfo.cpp:46

bool isPreIncrement(const MachineInstr &MI) const

Definition ARCInstrInfo.cpp:419

If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...

Definition ARCInstrInfo.cpp:69

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition ARCInstrInfo.cpp:322

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

Definition ARCInstrInfo.cpp:404

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

Return the inverse opcode of the specified Branch instruction.

Definition ARCInstrInfo.cpp:351

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition ARCInstrInfo.cpp:255

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Describe properties that are true of each instruction in the target description file.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

Representation of each machine instruction.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

MachineOperand class - Representation of each machine instruction operand.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ Define

This is an optimization pass for GlobalISel generic memory operations.

static bool isCondBranchOpcode(int Opc)

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

unsigned getKillRegState(bool B)

DWARFExpression::Operation Op

static bool isUncondBranchOpcode(int Opc)

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.