LLVM: lib/Target/ARC/ARCInstrInfo.h Source File (original) (raw)

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13#ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H

14#define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H

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19#define GET_INSTRINFO_HEADER

20#include "ARCGenInstrInfo.inc"

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22namespace llvm {

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24class ARCSubtarget;

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28 virtual void anchor();

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30public:

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41 int &FrameIndex) const override;

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49 int &FrameIndex) const override;

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56 bool AllowModify) const override;

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61 int *BytesAdded = nullptr) const override;

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64 int *BytesRemoved = nullptr) const override;

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68 bool KillSrc, bool RenamableDest = false,

69 bool RenamableSrc = false) const override;

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81 bool

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91 unsigned &BasePos,

92 unsigned &OffsetPos) const override;

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99};

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101}

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103#endif

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &, int *BytesAdded=nullptr) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override

bool isPostIncrement(const MachineInstr &MI) const override

Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override

If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....

MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const

const ARCRegisterInfo & getRegisterInfo() const

Definition ARCInstrInfo.h:33

ARCInstrInfo(const ARCSubtarget &)

bool isPreIncrement(const MachineInstr &MI) const

Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override

If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

Return the inverse opcode of the specified Branch instruction.

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

LLVM Value Representation.

This is an optimization pass for GlobalISel generic memory operations.