ARCRegisterInfo.cpp Source File (original) (raw)

31using namespace llvm;

33#define DEBUG_TYPE "arc-reg-info"

35#define GET_REGINFO_TARGET_DESC

36#include "ARCGenRegisterInfo.inc"

40 unsigned FrameReg, int Offset, int StackSize,

42 assert(RS && "Need register scavenger.");

46 unsigned BaseReg = FrameReg;

47 unsigned KillState = 0;

48 if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) {

55 return;

56 }

58 if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) {

60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass);

61 if (!BaseReg) {

65 MBB.getParent()->getSubtarget().getRegisterInfo();

66 BaseReg =

67 RS->scavengeRegisterBackwards(ARC::GPR32RegClass, II, false, SPAdj);

68 assert(BaseReg && "Register scavenging failed.");

70 << " for FrameReg=" << printReg(FrameReg, TRI)

71 << "+Offset=" << Offset << "\n");

72 (void)TRI;

73 RS->setRegUsed(BaseReg);

74 }

75 unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;

82 }

83 switch (MI.getOpcode()) {

84 case ARC::LD_rs9:

85 assert((Offset % 4 == 0) && "LD needs 4 byte alignment.");

86 [[fallthrough]];

87 case ARC::LDH_rs9:

88 case ARC::LDH_X_rs9:

89 assert((Offset % 2 == 0) && "LDH needs 2 byte alignment.");

90 [[fallthrough]];

91 case ARC::LDB_rs9:

92 case ARC::LDB_X_rs9:

95 .addReg(BaseReg, KillState)

98 break;

99 case ARC::ST_rs9:

100 assert((Offset % 4 == 0) && "ST needs 4 byte alignment.");

101 [[fallthrough]];

102 case ARC::STH_rs9:

103 assert((Offset % 2 == 0) && "STH needs 2 byte alignment.");

104 [[fallthrough]];

105 case ARC::STB_rs9:

109 .addReg(BaseReg, KillState)

112 break;

113 case ARC::GETFI:

120 break;

121 default:

123 }

124

125

127}

128

131

135

138 return CSR_ARC_SaveList;

139}

140

153

158

162

164 int SPAdj, unsigned FIOperandNum,

166 assert(SPAdj == 0 && "Unexpected");

169 int FrameIndex = FrameOp.getIndex();

170

178

182 LLVM_DEBUG(dbgs() << "FrameIndex : " << FrameIndex << "\n");

183 LLVM_DEBUG(dbgs() << "ObjSize : " << ObjSize << "\n");

185 LLVM_DEBUG(dbgs() << "StackSize : " << StackSize << "\n");

186 LLVM_DEBUG(dbgs() << "LocalFrameSize : " << LocalFrameSize << "\n");

187 (void)LocalFrameSize;

188

189

190 if (MI.isDebugValue()) {

192 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false );

193 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);

194 return false;

195 }

196

197

198 Offset += MI.getOperand(FIOperandNum + 1).getImm();

199

200

201

202

203

205 << "<--------->\n");

206

207 Register Reg = MI.getOperand(0).getReg();

208 assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand");

209

210 if (!TFI->hasFP(MF)) {

212 if (FrameIndex >= 0)

213 assert((Offset >= 0 && Offset < StackSize) && "SP Offset not in bounds.");

214 } else {

215 if (FrameIndex >= 0) {

217 "FP Offset not in bounds.");

218 }

219 }

221 ObjSize, RS, SPAdj);

222 return true;

223}

224

227 return TFI->hasFP(MF) ? ARC::FP : ARC::SP;

228}

229

233 return CSR_ARC_RegMask;

234}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static void replaceFrameIndex(MachineBasicBlock::iterator II, const ARCInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, int StackSize, int ObjSize, RegScavenger *RS, int SPAdj)

Definition ARCRegisterInfo.cpp:38

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file implements the BitVector class.

uint64_t IntrinsicInst * II

This file declares the machine register scavenger class.

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

MachineInstrBundleIterator< MachineInstr > iterator

uint64_t getStackSize() const

Return the number of bytes that must be allocated to hold all of the fixed size frame objects.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

int64_t getLocalFrameSize() const

Get the size of the local object blob.

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

bool needsFrameMoves() const

True if this function needs frame moves for debug or exceptions.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

Wrapper class representing virtual and physical registers.

bool hasFP(const MachineFunction &MF) const

hasFP - Return true if the specified function should have a dedicated frame pointer register.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Define

@ Kill

The last use of a register.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

unsigned getKillRegState(bool B)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override

Code Generation virtual methods...

Definition ARCRegisterInfo.cpp:137

BitVector getReservedRegs(const MachineFunction &MF) const override

Definition ARCRegisterInfo.cpp:141

const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override

Definition ARCRegisterInfo.cpp:231

bool useFPForScavengingIndex(const MachineFunction &MF) const override

Definition ARCRegisterInfo.cpp:159

Definition ARCRegisterInfo.cpp:225

bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

Definition ARCRegisterInfo.cpp:163

static bool needsFrameMoves(const MachineFunction &MF)

Return whether to emit frame moves.

Definition ARCRegisterInfo.cpp:132

ARCRegisterInfo(const ARCSubtarget &)

Definition ARCRegisterInfo.cpp:129

bool requiresRegisterScavenging(const MachineFunction &MF) const override

Definition ARCRegisterInfo.cpp:154