LLVM: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h Source File (original) (raw)

1

2

3

4

5

6

7

8

9#ifndef LLVM_LIB_TARGET_ARM_ARMASMBACKEND_H

10#define LLVM_LIB_TARGET_ARM_ARMASMBACKEND_H

11

17

18namespace llvm {

19

21public:

24

28

30

32

34

39

44

46

49

52

55 bool) const override;

56

59

62

64};

65}

66

67#endif

PowerPC TLS Dynamic Call Fixup

const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const

unsigned getPointerSize() const

Definition ARMAsmBackend.h:63

bool mayNeedRelaxation(unsigned Opcode, ArrayRef< MCOperand > Operands, const MCSubtargetInfo &STI) const override

Check whether the given instruction (encoded as Opcode+Operands) may need relaxation.

ARMAsmBackend(const Target &T, llvm::endianness Endian)

Definition ARMAsmBackend.h:22

bool fixupNeedsRelaxationAdvanced(const MCFragment &, const MCFixup &, const MCValue &, uint64_t, bool) const override

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...

void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, uint8_t *Data, uint64_t Value, bool IsResolved) override

bool hasNOP(const MCSubtargetInfo *STI) const

Definition ARMAsmBackend.h:25

MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override

Get information on a fixup kind.

unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const

std::optional< bool > evaluateFixup(const MCFragment &, MCFixup &, MCValue &, uint64_t &) override

unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo *STI) const

bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override

Write an (optimal) nop sequence of Count bytes to the given output.

std::optional< MCFixupKind > getFixupKind(StringRef Name) const override

Map a relocation name used in .reloc to a fixup kind.

void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override

Relax the instruction in the given fragment to the next wider instruction.

bool shouldForceRelocation(const MCFixup &Fixup, const MCValue &Target)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

const llvm::endianness Endian

MCAsmBackend(llvm::endianness Endian)

Context object for machine code objects.

Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...

Instances of this class represent a single low-level machine instruction.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

StringRef - Represent a constant reference to a string, i.e.

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

This is an optimization pass for GlobalISel generic memory operations.

uint16_t MCFixupKind

Extensible enumeration to represent the type of a fixup.

FunctionAddr VTableAddr Count

FunctionAddr VTableAddr uintptr_t uintptr_t Data

DWARFExpression::Operation Op

Target independent information on a fixup kind.