LLVM: lib/Target/ARM/ARMBaseInstrInfo.h File Reference (original) (raw)
Functions
static std::array< MachineOperand, 2 >
llvm::predOps (ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static MachineOperand
llvm::condCodeOp (unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
static MachineOperand
llvm::t1CondCodeOp (bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
static bool
llvm::isUncondBranchOpcode (int Opc)
static bool
llvm::isVPTOpcode (int Opc)
static unsigned
llvm::VCMPOpcodeToVPT (unsigned Opcode)
static bool
llvm::isCondBranchOpcode (int Opc)
static bool
llvm::isJumpTableBranchOpcode (int Opc)
static bool
llvm::isIndirectBranchOpcode (int Opc)
static bool
llvm::isIndirectCall (const MachineInstr &MI)
static bool
llvm::isIndirectControlFlowNotComingBack (const MachineInstr &MI)
static bool
llvm::isSpeculationBarrierEndBBOpcode (int Opc)
static bool
llvm::isPopOpcode (int Opc)
static bool
llvm::isPushOpcode (int Opc)
static bool
llvm::isSubImmOpcode (int Opc)
static bool
llvm::isMovRegOpcode (int Opc)
static bool
llvm::isValidCoprocessorNumber (unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instructions like CDP.
static bool
llvm::isSEHInstruction (const MachineInstr &MI)
llvm::getInstrPredicate (const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
llvm::getMatchingCondBranchOpcode (unsigned Opc)
llvm::convertAddSubFlagsOpcode (unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
void
llvm::emitARMRegPlusImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea destreg = basereg + immediate in ARM / Thumb2 code.
void
llvm::emitT2RegPlusImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
void
llvm::emitThumbRegPlusImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immediate in Thumb code.
llvm::tryFoldSPUpdateIntoPushPop (const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the stack by an additional NumBytes.
llvm::rewriteARMFrameIndex (MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
llvm::rewriteT2FrameIndex (MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
llvm::registerDefinedBetween (unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
llvm::findCMPToFoldIntoCBZ (MachineInstr *Br, const TargetRegisterInfo *TRI)
Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCBNZ.
void
llvm::addUnpredicatedMveVpredNOp (MachineInstrBuilder &MIB)
void
llvm::addUnpredicatedMveVpredROp (MachineInstrBuilder &MIB, Register DestReg)
void
llvm::addPredicatedMveVpredNOp (MachineInstrBuilder &MIB, unsigned Cond)
void
llvm::addPredicatedMveVpredROp (MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)
llvm::ConstantMaterializationCost (unsigned Val, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns the number of instructions required to materialize the given constant in a register, or 3 if a literal pool load is needed.
llvm::HasLowerConstantMaterializationCost (unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns true if Val1 has a lower Constant Materialization Cost than Val2.
int
llvm::getAddSubImmediate (MachineInstr &MI)
llvm::isLegalAddressImm (unsigned Opcode, int Imm, const TargetInstrInfo *TII)
llvm::isGather (IntrinsicInst *IntInst)
llvm::isScatter (IntrinsicInst *IntInst)
llvm::isGatherScatter (IntrinsicInst *IntInst)
llvm::getBLXOpcode (const MachineFunction &MF)
llvm::gettBLXrOpcode (const MachineFunction &MF)