LLVM: lib/Target/ARM/ARMFeatures.h Source File (original) (raw)
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13#ifndef LLVM_LIB_TARGET_ARM_ARMFEATURES_H
14#define LLVM_LIB_TARGET_ARM_ARMFEATURES_H
15
17
18namespace llvm {
19
20template
22
23template
25 switch (Instr->getOpcode()) {
26 default:
27 return false;
28 case ARM::tADC:
29 case ARM::tADDi3:
30 case ARM::tADDi8:
31 case ARM::tADDrr:
32 case ARM::tAND:
33 case ARM::tASRri:
34 case ARM::tASRrr:
35 case ARM::tBIC:
36 case ARM::tEOR:
37 case ARM::tLSLri:
38 case ARM::tLSLrr:
39 case ARM::tLSRri:
40 case ARM::tLSRrr:
41 case ARM::tMOVi8:
42 case ARM::tMUL:
43 case ARM::tMVN:
44 case ARM::tORR:
45 case ARM::tROR:
46 case ARM::tRSB:
47 case ARM::tSBC:
48 case ARM::tSUBi3:
49 case ARM::tSUBi8:
50 case ARM::tSUBrr:
51
53 case ARM::tADDrSPi:
54 case ARM::tCMNz:
55 case ARM::tCMPi8:
56 case ARM::tCMPr:
57 case ARM::tLDRBi:
58 case ARM::tLDRBr:
59 case ARM::tLDRHi:
60 case ARM::tLDRHr:
61 case ARM::tLDRSB:
62 case ARM::tLDRSH:
63 case ARM::tLDRi:
64 case ARM::tLDRr:
65 case ARM::tLDRspi:
66 case ARM::tSTRBi:
67 case ARM::tSTRBr:
68 case ARM::tSTRHi:
69 case ARM::tSTRHr:
70 case ARM::tSTRi:
71 case ARM::tSTRr:
72 case ARM::tSTRspi:
73 case ARM::tTST:
74 return true;
75
76 case ARM::tADDspr:
77 case ARM::tBLXr:
78 case ARM::tBLXr_noip:
79 return Instr->getOperand(2).getReg() != ARM::PC;
80
81
82 case ARM::tADDrSP:
83 case ARM::tBX:
84 return Instr->getOperand(0).getReg() != ARM::PC;
85 case ARM::tADDhirr:
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(2).getReg() != ARM::PC;
88 case ARM::tCMPhir:
89 case ARM::tMOVr:
90 return Instr->getOperand(0).getReg() != ARM::PC &&
91 Instr->getOperand(1).getReg() != ARM::PC;
92 }
93}
94
95}
96
97#endif
InstrType
This represents what is and is not supported when finding similarity in Instructions.
This is an optimization pass for GlobalISel generic memory operations.
bool IsCPSRDead(const InstrType *Instr)
bool isV8EligibleForIT(const InstrType *Instr)
Definition ARMFeatures.h:24