AVRISelLowering.h Source File (original) (raw)

14#ifndef LLVM_AVR_ISEL_LOWERING_H

15#define LLVM_AVR_ISEL_LOWERING_H

20namespace llvm {

27public:

31public:

46 unsigned AS,

60 EVT VT) const override;

70 const char *constraint) const override;

72 std::pair<unsigned, const TargetRegisterClass *>

80 std::vector &Ops,

93 unsigned ExpansionFactor) const override {

95 }

99private:

113

115 bool isVarArg,

118

124 bool isVarArg,

135

136protected:

138

139private:

141 bool Tiny) const;

149 unsigned Opcode, int Width) const;

150};

151

152}

153

154#endif

static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)

static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)

This file describes how to lower LLVM code to machine code.

static SDValue LowerCallResult(SDValue Chain, SDValue InGlue, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)

LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...

A specific AVR target MCU.

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

Replace a node with an illegal result type with a new node built out of custom code.

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override

Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const override

For most targets, an LLVM type must be broken down into multiple smaller types.

Definition AVRISelLowering.h:86

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

ConstraintType getConstraintType(StringRef Constraint) const override

Given a constraint, return the type of constraint it is for this target.

const AVRSubtarget & Subtarget

Definition AVRISelLowering.h:137

ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override

Definition AVRISelLowering.h:92

InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override

Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...

ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override

Examine constraint string and operand type and determine a weight value.

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition AVRISelLowering.h:32

bool softPromoteHalfType() const override

Definition AVRISelLowering.h:97

MVT::SimpleValueType getCmpLibcallReturnType() const override

Return the ValueType for comparison libcalls.

Definition AVRISelLowering.h:36

Return the register ID of the name passed in.

AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

Lower the specified operand into the Ops vector.

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override

Return the ValueType of the result of SETCC operations.

bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override

Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...

A generic AVR implementation.

A parsed version of the target data layout string in and methods for querying it.

This is an important class for using LLVM in a threaded context.

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

ShiftLegalizationStrategy

Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...

TargetLowering(const TargetLowering &)=delete

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

MemIndexedMode

MemIndexedMode enum - This enum defines the load / store indexed addressing modes.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

This is an optimization pass for GlobalISel generic memory operations.

DWARFExpression::Operation Op

This structure contains all information that is necessary for lowering calls.