AVRRegisterInfo.cpp Source File (original) (raw)

27#define GET_REGINFO_TARGET_DESC

28#include "AVRGenRegisterInfo.inc"

30namespace llvm {

38 if (STI.hasTinyEncoding())

40 : CSR_NormalTiny_SaveList;

41 else

43 : CSR_Normal_SaveList;

44}

50 return STI.hasTinyEncoding() ? CSR_NormalTiny_RegMask : CSR_Normal_RegMask;

51}

71 for (unsigned Reg = AVR::R2; Reg <= AVR::R17; Reg++)

74 for (unsigned Reg = AVR::R3R2; Reg <= AVR::R18R17; Reg++)

76 }

92}

98 if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {

99 return &AVR::DREGSRegClass;

100 }

101

102 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {

103 return &AVR::GPR8RegClass;

104 }

105

107}

108

109

113 int Opcode = MI.getOpcode();

114

115

116 if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {

117 return;

118 }

119

120

121

122 if (DstReg != MI.getOperand(0).getReg()) {

123 return;

124 }

125

126

127 switch (Opcode) {

128 case AVR::SUBIWRdK:

129 Offset += -MI.getOperand(2).getImm();

130 break;

131 case AVR::ADIWRdK:

132 Offset += MI.getOperand(2).getImm();

133 break;

134 }

135

136

137 II++;

138 MI.eraseFromParent();

139}

140

142 int SPAdj, unsigned FIOperandNum,

144 assert(SPAdj == 0 && "Unexpected SPAdj value");

145

155 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

157

158

160

161 Offset += MI.getOperand(FIOperandNum + 1).getImm();

162

163

164

165

166 if (MI.getOpcode() == AVR::FRMIDX) {

167 Register DstReg = MI.getOperand(0).getReg();

168 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");

169

170

171 if (STI.hasMOVW()) {

173 } else {

175 splitReg(DstReg, DstLoReg, DstHiReg);

178 }

179

181

182

183 unsigned Opcode;

184

185 II++;

186

187

188

189

190

191

192

193

194

195 if (II != MBB.end())

197

198

199 switch (DstReg) {

200 case AVR::R25R24:

201 case AVR::R27R26:

202 case AVR::R31R30: {

204 Opcode = AVR::ADIWRdK;

205 break;

206 }

207 [[fallthrough]];

208 }

209 default: {

210

211 Opcode = AVR::SUBIWRdK;

213 break;

214 }

215 }

216

220 New->getOperand(3).setIsDead();

221

222 MI.eraseFromParent();

223

224 return false;

225 }

226

227

228

229

230

231

232 int MaxOffset = STI.hasTinyEncoding() ? 0 : 62;

233

234

235

236

237

238 if (Offset > MaxOffset) {

239 unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;

240 int AddOffset = Offset - MaxOffset;

241

242

243 if ((Offset - MaxOffset) > 63 || !STI.hasADDSUBIW()) {

244 AddOpc = AVR::SUBIWRdK;

245 SubOpc = AVR::SUBIWRdK;

246 AddOffset = -AddOffset;

247 }

248

249

250

251

252

255

259 New->getOperand(3).setIsDead();

260

261

265

266

267

268 BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)

271

273 }

274

275 MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);

277 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);

278 return false;

279}

280

283 if (TFI->hasFP(MF)) {

284

285 return AVR::R28;

286 }

287

288 return AVR::SP;

289}

290

293

294

295

296 return &AVR::PTRDISPREGSRegClass;

297}

298

301 assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");

302

303 LoReg = getSubReg(Reg, AVR::sub_lo);

304 HiReg = getSubReg(Reg, AVR::sub_hi);

305}

306

311 if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {

312 return false;

313 }

314

316 NewRC, LIS);

317}

318

319}

static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file implements the BitVector class.

const HexagonInstrInfo * TII

uint64_t IntrinsicInst * II

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

Contains AVR-specific information for each MachineFunction.

bool isInterruptOrSignalHandler() const

Checks if the function is some form of interrupt service routine.

const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override

Definition AVRRegisterInfo.cpp:95

AVRRegisterInfo()

Definition AVRRegisterInfo.cpp:32

bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

Stack Frame Processing Methods.

Definition AVRRegisterInfo.cpp:141

const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=nullptr) const override

Definition AVRRegisterInfo.cpp:35

BitVector getReservedRegs(const MachineFunction &MF) const override

Definition AVRRegisterInfo.cpp:53

bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override

Definition AVRRegisterInfo.cpp:307

const TargetRegisterClass * getPointerRegClass(unsigned Kind=0) const override

Definition AVRRegisterInfo.cpp:292

const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override

Definition AVRRegisterInfo.cpp:47

Definition AVRRegisterInfo.cpp:281

void splitReg(Register Reg, Register &LoReg, Register &HiReg) const

Splits a 16-bit DREGS register into the lo/hi register pair.

Definition AVRRegisterInfo.cpp:299

A specific AVR target MCU.

const TargetFrameLowering * getFrameLowering() const override

const AVRInstrInfo * getInstrInfo() const override

A generic AVR implementation.

const AVRSubtarget * getSubtargetImpl() const

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

uint64_t getStackSize() const

Return the number of bytes that must be allocated to hold all of the fixed size frame objects.

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

Information about stack frame layout on the target.

bool hasFP(const MachineFunction &MF) const

hasFP - Return true if the specified function should have a dedicated frame pointer register.

int getOffsetOfLocalArea() const

getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const

Subtarget Hooks.

virtual const TargetFrameLowering * getFrameLowering() const

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Kill

The last use of a register.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, Register DstReg)

Fold a frame offset shared between two add instructions into a single one.

Definition AVRRegisterInfo.cpp:110