LLVM: lib/CodeGen/AggressiveAntiDepBreaker.h Source File (original) (raw)
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16#ifndef LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
17#define LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
18
23#include
24#include
25#include
26
27namespace llvm {
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53 const unsigned NumTargetRegs;
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60 std::vector GroupNodes;
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66 std::vector GroupNodeIndices;
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69 std::multimap<MCRegister, RegisterReference> RegRefs;
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73 std::vector KillIndices;
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77 std::vector DefIndices;
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79 public:
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83 std::vector &GetKillIndices() { return KillIndices; }
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86 std::vector &GetDefIndices() { return DefIndices; }
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89 std::multimap<MCRegister, RegisterReference> &GetRegRefs() {
90 return RegRefs;
91 }
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99 void GetGroupRegs(
100 unsigned Group, std::vector &Regs,
101 std::multimap<MCRegister, AggressiveAntiDepState::RegisterReference>
102 *RegRefs);
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115 };
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149 unsigned InsertPosIndex,
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155 unsigned InsertPosIndex) override;
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162 using RenameOrderType = std::map<const TargetRegisterClass *, unsigned>;
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170 void GetPassthruRegs(MachineInstr &MI, std::set &PassthruRegs);
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172 void HandleLastUse(MCRegister Reg, unsigned KillIdx, const char *tag,
173 const char *header = nullptr,
174 const char *footer = nullptr);
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177 const std::set &PassthruRegs);
180 bool FindSuitableFreeRegisters(MCRegister SuperReg,
181 unsigned AntiDepGroupIndex,
182 RenameOrderType &RenameOrder,
183 std::map<MCRegister, MCRegister> &RenameMap);
184 };
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186}
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188#endif
This file implements the BitVector class.
#define LLVM_LIBRARY_VISIBILITY
void Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex) override
Update liveness information to account for the current instruction, which will not be scheduled.
AggressiveAntiDepBreaker & operator=(const AggressiveAntiDepBreaker &other)=delete
AggressiveAntiDepBreaker(const AggressiveAntiDepBreaker &other)=delete
void FinishBlock() override
Finish anti-dep breaking for a basic block.
unsigned BreakAntiDependencies(const std::vector< SUnit > &SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned InsertPosIndex, DbgValueVector &DbgValues) override
Identifiy anti-dependencies along the critical path of the ScheduleDAG and break them by renaming reg...
void StartBlock(MachineBasicBlock *BB) override
Initialize anti-dep breaking for a new basic block.
AggressiveAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
Contains all the state necessary for anti-dep breaking.
Definition AggressiveAntiDepBreaker.h:40
AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB)
std::vector< unsigned > & GetDefIndices()
Return the define indices.
Definition AggressiveAntiDepBreaker.h:86
std::vector< unsigned > & GetKillIndices()
Return the kill indices.
Definition AggressiveAntiDepBreaker.h:83
std::multimap< MCRegister, RegisterReference > & GetRegRefs()
Return the RegRefs map.
Definition AggressiveAntiDepBreaker.h:89
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
Wrapper class representing physical registers. Should be passed by value.
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SmallVectorImpl< const TargetRegisterClass * > RegClassVector
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Count
Information about a register reference within a liverange.
Definition AggressiveAntiDepBreaker.h:43
MachineOperand * Operand
The registers operand.
Definition AggressiveAntiDepBreaker.h:45
const TargetRegisterClass * RC
The register class.
Definition AggressiveAntiDepBreaker.h:48