LLVM: lib/Target/BPF/BPFInstrInfo.cpp Source File (original) (raw)
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21#include
22#include
23
24#define GET_INSTRINFO_CTOR_DTOR
25#include "BPFGenInstrInfo.inc"
26
27using namespace llvm;
28
31
35 Register SrcReg, bool KillSrc,
36 bool RenamableDest, bool RenamableSrc) const {
37 if (BPF::GPRRegClass.contains(DestReg, SrcReg))
40 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg))
43 else
45}
46
48 Register DstReg = MI->getOperand(0).getReg();
49 Register SrcReg = MI->getOperand(1).getReg();
50 uint64_t CopyLen = MI->getOperand(2).getImm();
51 uint64_t Alignment = MI->getOperand(3).getImm();
52 Register ScratchReg = MI->getOperand(4).getReg();
55 unsigned LdOpc, StOpc;
56
57 switch (Alignment) {
58 case 1:
59 LdOpc = BPF::LDB;
60 StOpc = BPF::STB;
61 break;
62 case 2:
63 LdOpc = BPF::LDH;
64 StOpc = BPF::STH;
65 break;
66 case 4:
67 LdOpc = BPF::LDW;
68 StOpc = BPF::STW;
69 break;
70 case 8:
71 LdOpc = BPF::LDD;
72 StOpc = BPF::STD;
73 break;
74 default:
76 }
77
78 unsigned IterationNum = CopyLen >> Log2_64(Alignment);
79 for(unsigned I = 0; I < IterationNum; ++I) {
86 }
87
88 unsigned BytesLeft = CopyLen & (Alignment - 1);
89 unsigned Offset = IterationNum * Alignment;
90 bool Hanging4Byte = BytesLeft & 0x4;
91 bool Hanging2Byte = BytesLeft & 0x2;
92 bool Hanging1Byte = BytesLeft & 0x1;
93 if (Hanging4Byte) {
99 }
100 if (Hanging2Byte) {
106 }
107 if (Hanging1Byte) {
112 }
113
115}
116
118 if (MI.getOpcode() == BPF::MEMCPY) {
119 expandMEMCPY(MI);
120 return true;
121 }
122
123 return false;
124}
125
128 Register SrcReg, bool IsKill, int FI,
135
136 if (RC == &BPF::GPRRegClass)
141 else if (RC == &BPF::GPR32RegClass)
146 else
148}
149
159
160 if (RC == &BPF::GPRRegClass)
162 else if (RC == &BPF::GPR32RegClass)
164 else
165 llvm_unreachable("Can't load this register from stack slot");
166}
167
172 bool AllowModify) const {
173
174
176 while (I != MBB.begin()) {
177 --I;
178 if (I->isDebugInstr())
179 continue;
180
181
182
183 if (!isUnpredicatedTerminator(*I))
184 break;
185
186
187
188 if (I->isIndirectBranch())
189 return true;
190
191
192
193 if (->isBranch())
194 return true;
195
196
197 if (I->getOpcode() == BPF::JMP) {
198 if (!AllowModify) {
199 TBB = I->getOperand(0).getMBB();
200 continue;
201 }
202
203
204 MBB.erase(std::next(I), MBB.end());
205 Cond.clear();
206 FBB = nullptr;
207
208
209 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
210 TBB = nullptr;
211 I->eraseFromParent();
213 continue;
214 }
215
216
217 TBB = I->getOperand(0).getMBB();
218 continue;
219 }
220
221 return true;
222 }
223
224 return false;
225}
226
232 int *BytesAdded) const {
233 assert(!BytesAdded && "code size not handled");
234
235
236 assert(TBB && "insertBranch must not be told to insert a fallthrough");
237
238 if (Cond.empty()) {
239
240 assert(!FBB && "Unconditional branch with multiple successors!");
242 return 1;
243 }
244
246}
247
249 int *BytesRemoved) const {
250 assert(!BytesRemoved && "code size not handled");
251
253 unsigned Count = 0;
254
255 while (I != MBB.begin()) {
256 --I;
257 if (I->isDebugInstr())
258 continue;
259 if (I->getOpcode() != BPF::JMP)
260 break;
261
262 I->eraseFromParent();
265 }
266
268}
269
271 if (MI.getOpcode() != BPF::JX)
272 return -1;
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281
282 Register Reg = MI.getOperand(0).getReg();
283 if (!Reg.isVirtual())
284 return -1;
286 if (Ldd == nullptr || Ldd->getOpcode() != BPF::LDD)
287 return -1;
288
290 if (!Reg.isVirtual())
291 return -1;
293 if (Add == nullptr || Add->getOpcode() != BPF::ADD_rr)
294 return -1;
295
296 Reg = Add->getOperand(1).getReg();
297 if (!Reg.isVirtual())
298 return -1;
300 if (LDimm64 == nullptr || LDimm64->getOpcode() != BPF::LD_imm64)
301 return -1;
302
305 return -1;
306
308}
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition BPFInstrInfo.cpp:227
int getJumpTableIndex(const MachineInstr &MI) const override
Definition BPFInstrInfo.cpp:270
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
Definition BPFInstrInfo.cpp:32
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Definition BPFInstrInfo.cpp:126
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Definition BPFInstrInfo.cpp:150
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition BPFInstrInfo.cpp:168
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition BPFInstrInfo.cpp:117
BPFInstrInfo(const BPFSubtarget &STI)
Definition BPFInstrInfo.cpp:29
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition BPFInstrInfo.cpp:248
LLVM_ABI instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineInstrBundleIterator< MachineInstr > iterator
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Define
Register definition.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
FunctionAddr VTableAddr Count
unsigned getKillRegState(bool B)