BitTracker.cpp Source File (original) (raw)

66using namespace llvm;

70namespace {

74 struct printv {

75 printv(unsigned r) : R(r) {}

77 unsigned R;

78 };

81 if (PV.R)

82 OS << 'v' << Register(PV.R).virtRegIndex();

83 else

84 OS << 's';

85 return OS;

86 }

88}

90namespace llvm {

93 switch (BV.Type) {

94 case BT::BitValue::Top:

95 OS << 'T';

96 break;

97 case BT::BitValue::Zero:

98 OS << '0';

99 break;

100 case BT::BitValue::One:

101 OS << '1';

102 break;

103 case BT::BitValue::Ref:

104 OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']';

105 break;

106 }

107 return OS;

108 }

109

111 unsigned n = RC.Bits.size();

112 OS << "{ w:" << n;

113

114

115

116

117 unsigned Start = 0;

118 bool SeqRef = false;

119 bool ConstRef = false;

120

121 for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) {

124 bool IsRef = (V.Type == BT::BitValue::Ref);

125

126 if (!IsRef && V == SV)

127 continue;

128 if (IsRef && SV.Type == BT::BitValue::Ref && V.RefI.Reg == SV.RefI.Reg) {

129 if (Start+1 == i) {

130 SeqRef = (V.RefI.Pos == SV.RefI.Pos+1);

131 ConstRef = (V.RefI.Pos == SV.RefI.Pos);

132 }

133 if (SeqRef && V.RefI.Pos == SV.RefI.Pos+(i-Start))

134 continue;

135 if (ConstRef && V.RefI.Pos == SV.RefI.Pos)

136 continue;

137 }

138

139

140

141 OS << " [" << Start;

142 unsigned Count = i - Start;

143 if (Count == 1) {

144 OS << "]:" << SV;

145 } else {

146 OS << '-' << i-1 << "]:";

147 if (SV.Type == BT::BitValue::Ref && SeqRef)

148 OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-'

150 else

151 OS << SV;

152 }

153 Start = i;

154 SeqRef = ConstRef = false;

155 }

156

157 OS << " [" << Start;

158 unsigned Count = n - Start;

159 if (n-Start == 1) {

160 OS << "]:" << RC[Start];

161 } else {

162 OS << '-' << n-1 << "]:";

164 if (SV.Type == BT::BitValue::Ref && SeqRef)

165 OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-'

167 else

168 OS << SV;

169 }

170 OS << " }";

171

172 return OS;

173 }

174

175}

176

178 for (const std::pair<unsigned, RegisterCell> P : Map)

179 dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n";

180}

181

185

189

190

191

192

193

194

195

197

198

201 for (uint16_t i = 0, n = Bits.size(); i < n; ++i) {

204 }

206}

207

208

212

214

215

216 assert(B > E || E-B+1 == RC.width());

217 assert(B <= E || E+(W-B)+1 == RC.width());

218 if (B <= E) {

219 for (uint16_t i = 0; i <= E-B; ++i)

220 Bits[i+B] = RC[i];

221 } else {

222 for (uint16_t i = 0; i < W-B; ++i)

223 Bits[i+B] = RC[i];

224 for (uint16_t i = 0; i <= E; ++i)

225 Bits[i] = RC[i+(W-B)];

226 }

227 return *this;

228}

229

233 if (B <= E) {

235 for (uint16_t i = B; i <= E; ++i)

236 RC.Bits[i-B] = Bits[i];

237 return RC;

238 }

239

241 for (uint16_t i = 0; i < W-B; ++i)

242 RC.Bits[i] = Bits[i+B];

243 for (uint16_t i = 0; i <= E; ++i)

244 RC.Bits[i+(W-B)] = Bits[i];

245 return RC;

246}

247

249

250

252 Sh = Sh % W;

253 if (Sh == 0)

254 return *this;

255

257

258 for (uint16_t i = 0; i < W-Sh; ++i)

259 Tmp[i] = Bits[i];

260

261 for (uint16_t i = 0; i < Sh; ++i)

262 Bits[i] = Bits[W-Sh+i];

263

264 for (uint16_t i = 0; i < W-Sh; ++i)

265 Bits[i+Sh] = Tmp.Bits[i];

266 return *this;

267}

268

272 while (B < E)

273 Bits[B++] = V;

274 return *this;

275}

276

278

279

281 Bits.resize(W+WRC);

282 for (uint16_t i = 0; i < WRC; ++i)

283 Bits[i+W] = RC.Bits[i];

284 return *this;

285}

286

291 while (C < W && Bits[C] == V)

292 C++;

293 return C;

294}

295

300 while (C < W && Bits[W-(C+1)] == V)

301 C++;

302 return C;

303}

304

305bool BT::RegisterCell::operator== (const RegisterCell &RC) const {

307 if (RC.Bits.size() != W)

308 return false;

309 for (uint16_t i = 0; i < W; ++i)

310 if (Bits[i] != RC[i])

311 return false;

312 return true;

313}

314

316 for (unsigned i = 0, n = width(); i < n; ++i) {

320 }

321 return *this;

322}

323

325

326

327

328

329

330

331

332

335 return TRI.getRegSizeInBits(VC);

336 }

341}

342

346

347

348

351

353

354

358

359 CellMapType::const_iterator F = M.find(RR.Reg);

360 if (F != M.end()) {

361 if (!RR.Sub)

362 return F->second;

364 return F->second.extract(M);

365 }

366

368}

369

372

373

374

376 return;

377 assert(RR.Sub == 0 && "Unexpected sub-register in definition");

378

380}

381

382

383bool BT::MachineEvaluator::isInt(const RegisterCell &A) const {

385 for (uint16_t i = 0; i < W; ++i)

386 if ([i].is(0) && [i].is(1))

387 return false;

388 return true;

389}

390

391

396 for (uint16_t i = 0; i < W; ++i) {

397 Val <<= 1;

398 Val |= A[i].is(1);

399 }

400 return Val;

401}

402

403

404

405

406

409

410 for (uint16_t i = 0; i < W; ++i) {

412 V >>= 1;

413 }

414 return Res;

415}

416

420 assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow");

422 for (uint16_t i = 0; i < BW; ++i)

423 Res[i] = A[i];

424 return Res;

425}

426

432 bool Carry = false;

434 for (I = 0; I < W; ++I) {

437 if (!V1.num() || !V2.num())

438 break;

439 unsigned S = bool(V1) + bool(V2) + Carry;

441 Carry = (S > 1);

442 }

443 for (; I < W; ++I) {

446

447

448 if (V1.is(Carry))

450 else if (V2.is(Carry))

452 else

453 break;

454 }

455 for (; I < W; ++I)

457 return Res;

458}

459

465 bool Borrow = false;

467 for (I = 0; I < W; ++I) {

470 if (!V1.num() || !V2.num())

471 break;

472 unsigned S = bool(V1) - bool(V2) - Borrow;

474 Borrow = (S > 1);

475 }

476 for (; I < W; ++I) {

479 if (V1.is(Borrow)) {

481 break;

482 }

483 if (V2.is(Borrow))

485 else

486 break;

487 }

488 for (; I < W; ++I)

490 return Res;

491}

492

502

512

517 Res.rol(Sh);

519 return Res;

520}

521

527 Res.rol(W-Sh);

529 return Res;

530}

531

538 Res.rol(W-Sh);

539 Res.fill(W-Sh, W, Sign);

540 return Res;

541}

542

548 for (uint16_t i = 0; i < W; ++i) {

551 if (V1.is(1))

553 else if (V2.is(1))

555 else if (V1.is(0) || V2.is(0))

557 else if (V1 == V2)

558 Res[i] = V1;

559 else

561 }

562 return Res;

563}

564

570 for (uint16_t i = 0; i < W; ++i) {

573 if (V1.is(1) || V2.is(1))

575 else if (V1.is(0))

577 else if (V2.is(0))

579 else if (V1 == V2)

580 Res[i] = V1;

581 else

583 }

584 return Res;

585}

586

592 for (uint16_t i = 0; i < W; ++i) {

595 if (V1.is(0))

597 else if (V2.is(0))

599 else if (V1 == V2)

601 else

603 }

604 return Res;

605}

606

610 for (uint16_t i = 0; i < W; ++i) {

612 if (V.is(0))

614 else if (V.is(1))

616 else

618 }

619 return Res;

620}

621

629

637

641

642

643 if ((C < AW && A1[AW-1-C].num()) || C == AW)

644 return eIMM(C, W);

646}

647

651

652

653 if ((C < AW && A1[C].num()) || C == AW)

654 return eIMM(C, W);

656}

657

663 BitValue Sign = Res[FromN-1];

664

665 Res.fill(FromN, W, Sign);

666 return Res;

667}

668

677

682 if (B == E)

686

687 return Res;

688}

689

693 (void)W1;

694 assert(AtN < W1 && AtN+W2 <= W1);

695

697 if (W2 > 0)

699 return Res;

700}

701

703 assert(Sub == 0 && "Generic BitTracker::mask called for Sub != 0");

705 assert(W > 0 && "Cannot generate mask for empty register");

707}

708

711 return TRI.getRegSizeInBits(PC);

712}

713

717 unsigned Opc = MI.getOpcode();

718 switch (Opc) {

719 case TargetOpcode::REG_SEQUENCE: {

723 unsigned SS = MI.getOperand(2).getImm();

725 unsigned ST = MI.getOperand(4).getImm();

727

732 putCell(RD, Res, Outputs);

733 break;

734 }

735

736 case TargetOpcode::COPY: {

737

738

749 putCell(RD, Res, Outputs);

750 break;

751 }

752

753 default:

754 return false;

755 }

756

757 return true;

758}

759

760bool BT::UseQueueType::Cmp::operator()(const MachineInstr *InstA,

762

763

764

765

766 if (InstA == InstB)

767 return false;

770 if (BA != BB) {

771

772

774 }

775

777 auto F = Dist.find(MI);

778 if (F != Dist.end())

779 return F->second;

782 unsigned D = std::distance(I, E);

783 Dist.insert(std::make_pair(MI, D));

784 return D;

785 };

786

787 return getDist(InstA) > getDist(InstB);

788}

789

790

791

792void BT::visitPHI(const MachineInstr &PI) {

794 if (Trace)

796

797 const MachineOperand &MD = PI.getOperand(0);

798 assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition");

800 uint16_t DefBW = ME.getRegBitWidth(DefRR);

801

804 return;

805

807

808 for (unsigned i = 1, n = PI.getNumOperands(); i < n; i += 2) {

810 int PredN = PB->getNumber();

811 if (Trace)

814 if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {

815 if (Trace)

816 dbgs() << " not executable\n";

817 continue;

818 }

819

822 if (Trace)

823 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)

824 << " cell: " << ResC << "\n";

825 Changed |= DefC.meet(ResC, DefRR.Reg);

826 }

827

829 if (Trace)

830 dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub)

831 << " cell: " << DefC << "\n";

832 ME.putCell(DefRR, DefC, Map);

833 visitUsesOf(DefRR.Reg);

834 }

835}

836

837void BT::visitNonBranch(const MachineInstr &MI) {

838 if (Trace)

840 if (MI.isDebugInstr())

841 return;

842 assert(.isBranch() && "Unexpected branch instruction");

843

845 bool Eval = ME.evaluate(MI, Map, ResMap);

846

847 if (Trace && Eval) {

848 for (const MachineOperand &MO : MI.operands()) {

849 if (!MO.isReg() || !MO.isUse())

850 continue;

852 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)

853 << " cell: " << ME.getCell(RU, Map) << "\n";

854 }

855 dbgs() << "Outputs:\n";

856 for (const std::pair<const unsigned, RegisterCell> &P : ResMap) {

858 dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: "

859 << ME.getCell(RD, ResMap) << "\n";

860 }

861 }

862

863

864

865 for (const MachineOperand &MO : MI.operands()) {

866

867 if (!MO.isReg() || !MO.isDef())

868 continue;

870 assert(RD.Sub == 0 && "Unexpected sub-register in definition");

871 if (!RD.Reg.isVirtual())

872 continue;

873

875 if (!Eval || ResMap.count(RD.Reg) == 0) {

876

877 uint16_t DefBW = ME.getRegBitWidth(RD);

879 if (RefC != ME.getCell(RD, Map)) {

880 ME.putCell(RD, RefC, Map);

882 }

883 } else {

886

887

888

889

890

891

892

893 for (uint16_t i = 0, w = DefC.width(); i < w; ++i) {

895

897 continue;

898

899 if (V == ResC[i])

900 continue;

901 V = ResC[i];

903 }

905 ME.putCell(RD, DefC, Map);

906 }

908 visitUsesOf(RD.Reg);

909 }

910}

911

912void BT::visitBranchesFrom(const MachineInstr &BI) {

913 const MachineBasicBlock &B = *BI.getParent();

916 bool FallsThrough = true, DefaultToAll = false;

917 int ThisN = B.getNumber();

918

919 do {

920 BTs.clear();

921 const MachineInstr &MI = *It;

922 if (Trace)

924 assert(MI.isBranch() && "Expecting branch instruction");

925 InstrExec.insert(&MI);

926 bool Eval = ME.evaluate(MI, Map, BTs, FallsThrough);

927 if (!Eval) {

928

929

930 DefaultToAll = true;

931 FallsThrough = true;

932 if (Trace)

933 dbgs() << " failed to evaluate: will add all CFG successors\n";

934 } else if (!DefaultToAll) {

935

936 if (Trace) {

937 dbgs() << " adding targets:";

938 for (const MachineBasicBlock *BT : BTs)

940 if (FallsThrough)

941 dbgs() << "\n falls through\n";

942 else

943 dbgs() << "\n does not fall through\n";

944 }

945 Targets.insert_range(BTs);

946 }

947 ++It;

948 } while (FallsThrough && It != End);

949

950 if (B.mayHaveInlineAsmBr())

951 DefaultToAll = true;

952

953 if (!DefaultToAll) {

954

955

956

957 for (const MachineBasicBlock *SB : B.successors()) {

958 if (SB->isEHPad())

959 Targets.insert(SB);

960 }

961 if (FallsThrough) {

964 if (Next != MF.end())

965 Targets.insert(&*Next);

966 }

967 } else {

968 Targets.insert_range(B.successors());

969 }

970

971 for (const MachineBasicBlock *TB : Targets)

972 FlowQ.push(CFGEdge(ThisN, TB->getNumber()));

973}

974

976 if (Trace)

977 dbgs() << "queuing uses of modified reg " << printReg(Reg, &ME.TRI)

978 << " cell: " << ME.getCell(Reg, Map) << '\n';

979

980 for (MachineInstr &UseI : MRI.use_nodbg_instructions(Reg))

981 UseQ.push(&UseI);

982}

983

985 return ME.getCell(RR, Map);

986}

987

989 ME.putCell(RR, RC, Map);

990}

991

992

993

995 assert(Map.count(OldRR.Reg) > 0 && "OldRR not present in map");

1000 (void)NME;

1001 assert((OME-OMB == NME-NMB) &&

1002 "Substituting registers of different lengths");

1003 for (std::pair<const unsigned, RegisterCell> &P : Map) {

1005 for (uint16_t i = 0, w = RC.width(); i < w; ++i) {

1008 continue;

1009 if (V.RefI.Pos < OMB || V.RefI.Pos > OME)

1010 continue;

1011 V.RefI.Reg = NewRR.Reg;

1012 V.RefI.Pos += NMB-OMB;

1013 }

1014 }

1015}

1016

1017

1018

1020 int BN = B->getNumber();

1022 return ReachedBB.count(BN);

1023}

1024

1025

1026

1028 assert(.isBranch() && "Only non-branches are allowed");

1029 InstrExec.insert(&MI);

1030 visitNonBranch(MI);

1031

1032 runUseQueue();

1033

1034

1035

1036 while (!FlowQ.empty())

1037 FlowQ.pop();

1038}

1039

1040void BT::reset() {

1041 EdgeExec.clear();

1042 InstrExec.clear();

1043 Map.clear();

1044 ReachedBB.clear();

1046}

1047

1048void BT::runEdgeQueue(BitVector &BlockScanned) {

1049 while (!FlowQ.empty()) {

1050 CFGEdge Edge = FlowQ.front();

1051 FlowQ.pop();

1052

1053 if (!EdgeExec.insert(Edge).second)

1054 return;

1055 ReachedBB.insert(Edge.second);

1056

1059

1060 while (It != End && It->isPHI()) {

1062 InstrExec.insert(&PI);

1063 visitPHI(PI);

1064 }

1065

1066

1067

1068

1069 if (BlockScanned[Edge.second])

1070 return;

1071 BlockScanned[Edge.second] = true;

1072

1073

1074 while (It != End && !It->isBranch()) {

1075 const MachineInstr &MI = *It++;

1076 InstrExec.insert(&MI);

1077 visitNonBranch(MI);

1078 }

1079

1080 if (It == End) {

1083 if (Next != MF.end() && B.isSuccessor(&*Next)) {

1084 int ThisN = B.getNumber();

1085 int NextN = Next->getNumber();

1086 FlowQ.push(CFGEdge(ThisN, NextN));

1087 }

1088 } else {

1089

1090

1091 visitBranchesFrom(*It);

1092 }

1093 }

1094}

1095

1096void BT::runUseQueue() {

1097 while (!UseQ.empty()) {

1098 MachineInstr &UseI = *UseQ.front();

1099 UseQ.pop();

1100

1101 if (!InstrExec.count(&UseI))

1102 continue;

1103 if (UseI.isPHI())

1104 visitPHI(UseI);

1106 visitNonBranch(UseI);

1107 else

1108 visitBranchesFrom(UseI);

1109 }

1110}

1111

1113 reset();

1114 assert(FlowQ.empty());

1115

1117 const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF);

1118

1119 unsigned MaxBN = 0;

1121 assert(B.getNumber() >= 0 && "Disconnected block");

1122 unsigned BN = B.getNumber();

1123 if (BN > MaxBN)

1124 MaxBN = BN;

1125 }

1126

1127

1128 BitVector BlockScanned(MaxBN+1);

1129

1130 int EntryN = Entry->getNumber();

1131

1132 FlowQ.push(CFGEdge(-1, EntryN));

1133

1134 while (!FlowQ.empty() || !UseQ.empty()) {

1135 runEdgeQueue(BlockScanned);

1136 runUseQueue();

1137 }

1138 UseQ.reset();

1139

1140 if (Trace)

1142}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file implements a class to represent arbitrary precision integral constant values and operations...

BitTracker BT

Definition BitTracker.cpp:68

This file implements the BitVector class.

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

This file contains the declarations for the subclasses of Constant, which represent the different fla...

Promote Memory to Register

PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)

std::pair< BasicBlock *, BasicBlock * > Edge

Class for arbitrary precision integers.

This is the shared class of boolean and integer constants.

const APInt & getValue() const

Return the constant as an APInt value reference.

Wrapper class representing physical registers. Should be passed by value.

MachineInstrBundleIterator< const MachineInstr > const_iterator

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

MachineBasicBlock * getBlockNumbered(unsigned N) const

getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...

BasicBlockListType::const_iterator const_iterator

Representation of each machine instruction.

const MachineBasicBlock * getParent() const

unsigned getNumOperands() const

Retuns the total number of operands.

bool isBranch(QueryType Type=AnyInBundle) const

Returns true if this is a conditional, unconditional, or indirect branch.

const MachineOperand & getOperand(unsigned i) const

unsigned getSubReg() const

MachineBasicBlock * getMBB() const

Wrapper class representing virtual and physical registers.

MCRegister asMCReg() const

Utility to check-convert this value to a MCRegister.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

std::pair< iterator, bool > insert(const ValueT &V)

void reserve(size_t Size)

Grow the DenseSet so that it can contain at least NumEntries items before resizing again.

This class implements an extremely fast bulk output stream that can only output to a stream.

@ C

The default llvm calling convention, compatible with C.

@ TB

TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before th...

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

FunctionAddr VTableAddr Count

@ Sub

Subtraction of integers.

FunctionAddr VTableAddr Next

raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

static BitValue ref(const BitValue &V)

bool is(unsigned T) const

static BitValue self(const BitRef &Self=BitRef())

const TargetRegisterInfo & TRI

RegisterCell eIMM(int64_t V, uint16_t W) const

Definition BitTracker.cpp:407

uint16_t getRegBitWidth(const RegisterRef &RR) const

Definition BitTracker.cpp:324

bool isInt(const RegisterCell &A) const

Definition BitTracker.cpp:383

MachineRegisterInfo & MRI

virtual const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const

virtual bool track(const TargetRegisterClass *RC) const

void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const

Definition BitTracker.cpp:370

virtual uint16_t getPhysRegBitWidth(MCRegister Reg) const

Definition BitTracker.cpp:709

RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const

Definition BitTracker.cpp:343

virtual BitMask mask(Register Reg, unsigned Sub) const

Definition BitTracker.cpp:702

static RegisterCell self(unsigned Reg, uint16_t Width)

static RegisterCell ref(const RegisterCell &C)

RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)

Definition BitTracker.cpp:269

RegisterCell extract(const BitMask &M) const

Definition BitTracker.cpp:230

RegisterCell & regify(unsigned R)

Definition BitTracker.cpp:315

uint16_t ct(bool B) const

Definition BitTracker.cpp:287

RegisterCell & insert(const RegisterCell &RC, const BitMask &M)

Definition BitTracker.cpp:209

static RegisterCell top(uint16_t Width)

uint16_t cl(bool B) const

Definition BitTracker.cpp:296

RegisterCell(uint16_t Width=DefaultBitN)

RegisterCell & rol(uint16_t Sh)

Definition BitTracker.cpp:248

SetVector< const MachineBasicBlock * > BranchTargetList

bool reached(const MachineBasicBlock *B) const

Definition BitTracker.cpp:1019

~BitTracker()

Definition BitTracker.cpp:186

void subst(RegisterRef OldRR, RegisterRef NewRR)

Definition BitTracker.cpp:994

void print_cells(raw_ostream &OS) const

Definition BitTracker.cpp:177

std::map< unsigned, RegisterCell > CellMapType

void put(RegisterRef RR, const RegisterCell &RC)

Definition BitTracker.cpp:988

BitTracker(const MachineEvaluator &E, MachineFunction &F)

Definition BitTracker.cpp:182

void visit(const MachineInstr &MI)

Definition BitTracker.cpp:1027

void run()

Definition BitTracker.cpp:1112

RegisterCell get(RegisterRef RR) const

Definition BitTracker.cpp:984