CSKYAsmBackend.cpp Source File (original) (raw)

18#define DEBUG_TYPE "csky-asmbackend"

20using namespace llvm;

22std::unique_ptr

25}

37 {"fixup_csky_pcrel_uimm16_scale4", 0, 32,

41 {"fixup_csky_pcrel_uimm8_scale4", 0, 32,

50 {"fixup_csky_got_imm18_scale4", 0, 32, 0}},

56 {"fixup_csky_plt_imm18_scale4", 0, 32, 0}},

60 {"fixup_csky_pcrel_uimm7_scale4", 0, 16,

64 {"fixup_csky_doffset_imm18", 0, 18, 0}},

66 {"fixup_csky_doffset_imm18_scale2", 0, 18, 0}},

68 {"fixup_csky_doffset_imm18_scale4", 0, 18, 0}}};

71 "Not all fixup kinds added to Infos array");

75 "Invalid kind!");

77 return Infos[Kind];

80 } else {

82 }

83}

87 switch (Fixup.getTargetKind()) {

88 default:

96 llvm_unreachable("Relocation should be unconditionally forced\n");

103 return Value & 0xffffffff;

106 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");

108 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned.");

109

110 return (Value >> 1) & 0xffff;

113 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");

115 Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned.");

116

117 return (Value >> 2) & 0xffff;

120 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");

122 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned.");

123

124 return (Value >> 1) & 0x3ffffff;

127 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");

129 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned.");

130

131 return (Value >> 1) & 0x3ffff;

134 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");

136 Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned.");

137

138 unsigned IMM4L = (Value >> 2) & 0xf;

139 unsigned IMM4H = (Value >> 6) & 0xf;

140

141 Value = (IMM4H << 21) | (IMM4L << 4);

143 }

146 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");

148 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned.");

149

150 return (Value >> 1) & 0x3ff;

152 if ((Value >> 2) > 0xfe)

153 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value.");

155 Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned.");

156

157 if ((Value >> 2) <= 0x7f) {

158 unsigned IMM5L = (Value >> 2) & 0x1f;

159 unsigned IMM2H = (Value >> 7) & 0x3;

160

161 Value = (1 << 12) | (IMM2H << 8) | IMM5L;

162 } else {

163 unsigned IMM5L = (~Value >> 2) & 0x1f;

164 unsigned IMM2H = (~Value >> 7) & 0x3;

165

166 Value = (IMM2H << 8) | IMM5L;

167 }

168

170 }

171}

172

177 const bool WasForced) const {

178

179

180

181

182 if (!Resolved && !WasForced)

183 return true;

184

186 switch (Fixup.getTargetKind()) {

187 default:

188 return false;

190 return !isShiftedInt<10, 1>(Offset);

192 return !isShiftedInt<16, 1>(Offset);

194 return !isShiftedInt<26, 1>(Offset);

196 return ((Value >> 2) > 0xfe) || (Value & 0x3);

197 }

198}

199

203 bool IsResolved,

207 return;

208 MCContext &Ctx = Asm.getContext();

211 return;

212

214

215

217

219 unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;

220

221 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");

222

223

224

227

228 if (IsLittleEndian && IsInstFixup && (NumBytes == 4)) {

233 } else {

234 for (unsigned I = 0; I != NumBytes; I++) {

235 unsigned Idx = IsLittleEndian ? I : (NumBytes - 1 - I);

237 }

238 }

239}

240

244 default:

245 return false;

246 case CSKY::JBR32:

247 case CSKY::JBT32:

248 case CSKY::JBF32:

249 case CSKY::JBSR32:

251 return false;

252 return true;

253 case CSKY::JBR16:

254 case CSKY::JBT16:

255 case CSKY::JBF16:

256 case CSKY::LRW16:

257 case CSKY::BR16:

258 return true;

259 }

260}

261

268 return true;

269 switch (Fixup.getTargetKind()) {

270 default:

271 break;

281 return true;

282 }

283

284 return false;

285}

286

289 return false;

290}

291

295

297 default:

300 case CSKY::LRW16:

304 break;

305 case CSKY::BR16:

308 break;

309 case CSKY::JBSR32:

312 break;

313 case CSKY::JBR32:

316 break;

317 case CSKY::JBT32:

318 case CSKY::JBF32:

319 Res.setOpcode(Inst.getOpcode() == CSKY::JBT32 ? CSKY::JBT_E : CSKY::JBF_E);

323 break;

324 case CSKY::JBR16:

328 break;

329 case CSKY::JBT16:

330 case CSKY::JBF16:

331

332 unsigned opcode;

334 opcode = Inst.getOpcode() == CSKY::JBT16 ? CSKY::JBT32 : CSKY::JBF32;

335 else

336 opcode = Inst.getOpcode() == CSKY::JBT16 ? CSKY::JBT_E : CSKY::JBF_E;

337

342 break;

343 }

344 Inst = std::move(Res);

345}

346

350 return true;

351}

352

358}

unsigned const MachineRegisterInfo * MRI

static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)

Analysis containing CSE Info

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")

This file defines the DenseMap class.

PowerPC TLS Dynamic Call Fixup

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override

Get information on a fixup kind.

bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override

Check whether the given instruction may need relaxation.

bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const override

Simple predicate for targets where !Resolved implies requiring relaxation.

void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override

Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...

bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override

Hook to check if a relocation is needed for some target specific reason.

void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override

Relax the instruction in the given fragment to the next wider instruction.

unsigned int getNumFixupKinds() const override

Get the number of target specific fixup kinds.

bool fixupNeedsRelaxationAdvanced(const MCAssembler &Asm, const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const bool WasForced) const override

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...

std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override

bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override

Write an (optimal) nop sequence of Count bytes to the given output.

Generic interface to target specific assembler backends.

const llvm::endianness Endian

virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const

Get information on a fixup kind.

Context object for machine code objects.

void reportError(SMLoc L, const Twine &Msg)

Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

This represents an "assembler immediate".

MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

raw_ostream & write_zeros(unsigned NumZeros)

write_zeros - Insert 'NumZeros' nulls.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ fixup_csky_pcrel_imm10_scale2

@ fixup_csky_pcrel_uimm7_scale4

@ fixup_csky_doffset_imm18_scale2

@ fixup_csky_pcrel_imm16_scale2

@ fixup_csky_pcrel_imm18_scale2

@ fixup_csky_doffset_imm18_scale4

@ fixup_csky_pcrel_uimm16_scale4

@ fixup_csky_plt_imm18_scale4

@ fixup_csky_pcrel_imm26_scale2

@ fixup_csky_got_imm18_scale4

@ fixup_csky_pcrel_uimm8_scale4

@ fixup_csky_doffset_imm18

This is an optimization pass for GlobalISel generic memory operations.

bool isUIntN(unsigned N, uint64_t x)

Checks if an unsigned integer fits into the given (dynamic) bit width.

MCAsmBackend * createCSKYAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

std::unique_ptr< MCObjectTargetWriter > createCSKYELFObjectWriter()

MCFixupKind

Extensible enumeration to represent the type of a fixup.

@ FirstLiteralRelocationKind

The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....

@ FK_Data_8

A eight-byte fixup.

@ FK_Data_1

A one-byte fixup.

@ FK_Data_4

A four-byte fixup.

@ FK_Data_2

A two-byte fixup.

bool isIntN(unsigned N, int64_t x)

Checks if an signed integer fits into the given (dynamic) bit width.

uint64_t alignTo(uint64_t Size, Align A)

Returns a multiple of A needed to store Size bytes.

Target independent information on a fixup kind.

@ FKF_IsAlignedDownTo32Bits

Should this fixup kind force a 4-byte aligned effective PC value?

@ FKF_IsPCRel

Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...