LLVM: lib/Target/CSKY/CSKYInstrInfo.h Source File (original) (raw)

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13#ifndef LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H

14#define LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H

15

18

19#define GET_INSTRINFO_HEADER

20#include "CSKYGenInstrInfo.inc"

21

22namespace llvm {

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24class CSKYRegisterInfo;

25class CSKYSubtarget;

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28 bool v2sf;

29 bool v2df;

30 bool v3sf;

31 bool v3df;

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33protected:

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36public:

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40 int &FrameIndex) const override;

42 int &FrameIndex) const override;

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56 bool KillSrc, bool RenamableDest = false,

57 bool RenamableSrc = false) const override;

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62 int *BytesAdded = nullptr) const override;

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67 bool AllowModify = false) const override;

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70 int *BytesRemoved = nullptr) const override;

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72 bool

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85};

86

87}

88

89#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

CSKYInstrInfo(const CSKYSubtarget &STI, const CSKYRegisterInfo &RI)

const CSKYSubtarget & STI

Definition CSKYInstrInfo.h:34

MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Register movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const

Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override

Register getGlobalBaseReg(MachineFunction &MF) const

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is an optimization pass for GlobalISel generic memory operations.