CSKYRegisterInfo.cpp Source File (original) (raw)

21#define GET_REGINFO_TARGET_DESC

22#include "CSKYGenRegisterInfo.inc"

24using namespace llvm;

34 return CSR_GPR_FPR64_RegMask;

36 return CSR_GPR_FPR32_RegMask;

37 return CSR_I32_RegMask;

38}

42 return TFI->hasFP(MF) ? CSKY::R8 : CSKY::R14;

43}

52 if (TFI->hasBP(MF))

53 markSuperRegs(Reserved, CSKY::R7);

55 if (TFI->hasFP(MF))

56 markSuperRegs(Reserved, CSKY::R8);

58 if (!STI.hasE2()) {

59 for (unsigned i = 0; i < 6; i++)

60 markSuperRegs(Reserved, CSKY::R8 + i);

61 }

63 markSuperRegs(Reserved, CSKY::R14);

64 markSuperRegs(Reserved, CSKY::R15);

67 for (unsigned i = 0; i < 10; i++)

68 markSuperRegs(Reserved, CSKY::R16 + i);

69 }

71 markSuperRegs(Reserved, CSKY::R26);

72 markSuperRegs(Reserved, CSKY::R27);

73 markSuperRegs(Reserved, CSKY::R28);

74 markSuperRegs(Reserved, CSKY::R29);

75 markSuperRegs(Reserved, CSKY::R30);

76 markSuperRegs(Reserved, CSKY::R31);

80}

83 return CSR_NoRegs_RegMask;

84}

91 return CSR_GPR_FPR64v3_ISR_SaveList;

93 return CSR_GPR_FPR32v3_ISR_SaveList;

95 return CSR_GPR_FPR64_ISR_SaveList;

97 return CSR_GPR_FPR32_ISR_SaveList;

98 return CSR_GPR_ISR_SaveList;

99 }

100

102 return CSR_GPR_FPR64_SaveList;

104 return CSR_GPR_FPR32_SaveList;

105 return CSR_I32_SaveList;

106}

107

112 unsigned i = 0;

113 for (; ->getOperand(i).isFI(); ++i) {

114 assert(i + 1 < MI->getNumOperands() &&

115 "Instr doesn't have FrameIndex operand!");

116 }

117

118 if (MI->getOpcode() == CSKY::ADDI32) {

120 return false;

122 MI->setDesc(TII->get(CSKY::SUBI32));

124 }

125

126 return true;

127 }

128

129 if (MI->getOpcode() == CSKY::ADDI16XZ)

130 return false;

131

133 return false;

134

135 unsigned NumBits = 0;

136 unsigned Scale = 1;

139 Scale = 1;

140 NumBits = 12;

141 break;

143 Scale = 2;

144 NumBits = 12;

145 break;

147 Scale = 4;

148 NumBits = 12;

149 break;

151 Scale = 1;

152 NumBits = 5;

153 break;

155 Scale = 2;

156 NumBits = 5;

157 break;

159 Scale = 4;

160 NumBits = 5;

161 break;

163 Scale = 4;

164 NumBits = 8;

165 break;

166 default:

168 }

169

170

171 if ((Offset & (Scale - 1)) != 0)

172 return false;

173

174 unsigned Mask = (1 << NumBits) - 1;

175 if ((unsigned)Offset <= Mask * Scale)

176 return true;

177

178

179 return false;

180}

181

183 int SPAdj, unsigned FIOperandNum,

185 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");

186

194

195 switch (MI->getOpcode()) {

196 default:

197 break;

198 case CSKY::RESTORE_CARRY: {

200 ? MRI.createVirtualRegister(&CSKY::GPRRegClass)

201 : MRI.createVirtualRegister(&CSKY::mGPRRegClass);

202

204 .add(MI->getOperand(1))

205 .add(MI->getOperand(2))

207

209 MI->getOperand(0).getReg())

212

213 MI = Temp;

214

216 break;

217 }

218 case CSKY::SPILL_CARRY: {

220 if (STI.hasE2()) {

221 NewReg = MRI.createVirtualRegister(&CSKY::GPRRegClass);

223 .add(MI->getOperand(0));

224 } else {

225 NewReg = MRI.createVirtualRegister(&CSKY::mGPRRegClass);

232 .addReg(MI->getOperand(0).getReg());

233

234 BuildMI(MBB, II, DL, TII->get(CSKY::BTSTI16), MI->getOperand(0).getReg())

237 }

238

241 .add(MI->getOperand(1))

242 .add(MI->getOperand(2))

244

246

247 break;

248 }

249 }

250

251 int FrameIndex = MI->getOperand(FIOperandNum).getIndex();

253 int Offset = getFrameLowering(MF)

254 ->getFrameIndexReference(MF, FrameIndex, FrameReg)

255 .getFixed() +

256 MI->getOperand(FIOperandNum + 1).getImm();

257

260 "Frame offsets outside of the signed 32-bit range not supported");

261

262 bool FrameRegIsKill = false;

266

267

270 TII->get(STI.hasE2() ? CSKY::ADDU32 : CSKY::ADDU16XZ), ScratchReg)

273

275 FrameReg = ScratchReg;

276 FrameRegIsKill = true;

277 }

278

280 (MI->getOpcode() == CSKY::ADDI32 || MI->getOpcode() == CSKY::ADDI16XZ)) {

281 MI->setDesc(TII->get(TargetOpcode::COPY));

282 MI->getOperand(FIOperandNum)

283 .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

284 MI->removeOperand(FIOperandNum + 1);

285 } else {

286 MI->getOperand(FIOperandNum)

287 .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);

288 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);

289 }

290 return false;

291}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static bool IsLegalOffset(const CSKYInstrInfo *TII, MachineInstr *MI, int &Offset)

Definition CSKYRegisterInfo.cpp:108

uint64_t IntrinsicInst * II

This file declares the machine register scavenger class.

bool hasBP(const MachineFunction &MF) const

BitVector getReservedRegs(const MachineFunction &MF) const override

Definition CSKYRegisterInfo.cpp:45

CSKYRegisterInfo()

Definition CSKYRegisterInfo.cpp:26

Definition CSKYRegisterInfo.cpp:40

const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID id) const override

Definition CSKYRegisterInfo.cpp:30

const uint32_t * getNoPreservedMask() const override

Definition CSKYRegisterInfo.cpp:82

bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override

Definition CSKYRegisterInfo.cpp:182

const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override

Definition CSKYRegisterInfo.cpp:87

bool hasHighRegisters() const

bool hasFPUv2SingleFloat() const

bool hasFPUv3SingleFloat() const

bool hasFPUv2DoubleFloat() const

bool hasFPUv3DoubleFloat() const

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

Describe properties that are true of each instruction in the target description file.

MachineInstrBundleIterator< MachineInstr > iterator

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

Representation of each machine instruction.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

Information about stack frame layout on the target.

bool hasFP(const MachineFunction &MF) const

hasFP - Return true if the specified function should have a dedicated frame pointer register.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Define

@ Kill

The last use of a register.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

unsigned getKillRegState(bool B)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...