Utils.h Source File (original) (raw)

14#ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H

15#define LLVM_CODEGEN_GLOBALISEL_UTILS_H

27#include

29namespace llvm {

56#define GISEL_VECREDUCE_CASES_ALL \

57 case TargetOpcode::G_VECREDUCE_SEQ_FADD: \

58 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \

59 case TargetOpcode::G_VECREDUCE_FADD: \

60 case TargetOpcode::G_VECREDUCE_FMUL: \

61 case TargetOpcode::G_VECREDUCE_FMAX: \

62 case TargetOpcode::G_VECREDUCE_FMIN: \

63 case TargetOpcode::G_VECREDUCE_FMAXIMUM: \

64 case TargetOpcode::G_VECREDUCE_FMINIMUM: \

65 case TargetOpcode::G_VECREDUCE_ADD: \

66 case TargetOpcode::G_VECREDUCE_MUL: \

67 case TargetOpcode::G_VECREDUCE_AND: \

68 case TargetOpcode::G_VECREDUCE_OR: \

69 case TargetOpcode::G_VECREDUCE_XOR: \

70 case TargetOpcode::G_VECREDUCE_SMAX: \

71 case TargetOpcode::G_VECREDUCE_SMIN: \

72 case TargetOpcode::G_VECREDUCE_UMAX: \

73 case TargetOpcode::G_VECREDUCE_UMIN:

75#define GISEL_VECREDUCE_CASES_NONSEQ \

76 case TargetOpcode::G_VECREDUCE_FADD: \

77 case TargetOpcode::G_VECREDUCE_FMUL: \

78 case TargetOpcode::G_VECREDUCE_FMAX: \

79 case TargetOpcode::G_VECREDUCE_FMIN: \

80 case TargetOpcode::G_VECREDUCE_FMAXIMUM: \

81 case TargetOpcode::G_VECREDUCE_FMINIMUM: \

82 case TargetOpcode::G_VECREDUCE_ADD: \

83 case TargetOpcode::G_VECREDUCE_MUL: \

84 case TargetOpcode::G_VECREDUCE_AND: \

85 case TargetOpcode::G_VECREDUCE_OR: \

86 case TargetOpcode::G_VECREDUCE_XOR: \

87 case TargetOpcode::G_VECREDUCE_SMAX: \

88 case TargetOpcode::G_VECREDUCE_SMIN: \

89 case TargetOpcode::G_VECREDUCE_UMAX: \

90 case TargetOpcode::G_VECREDUCE_UMIN:

97 const TargetInstrInfo &TII,

98 const RegisterBankInfo &RBI, Register Reg,

99 const TargetRegisterClass &RegClass);

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110 const MachineFunction &MF, const TargetRegisterInfo &TRI,

111 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,

112 const RegisterBankInfo &RBI, MachineInstr &InsertPt,

113 const TargetRegisterClass &RegClass, MachineOperand &RegMO);

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126 const MachineFunction &MF, const TargetRegisterInfo &TRI,

127 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,

128 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,

129 MachineOperand &RegMO, unsigned OpIdx);

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141 const TargetInstrInfo &TII,

142 const TargetRegisterInfo &TRI,

143 const RegisterBankInfo &RBI);

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148 MachineRegisterInfo &MRI);

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153 const MachineRegisterInfo &MRI);

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158 MachineOptimizationRemarkEmitter &MORE,

159 MachineOptimizationRemarkMissed &R);

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162 MachineOptimizationRemarkEmitter &MORE,

163 const char *PassName, StringRef Msg,

164 const MachineInstr &MI);

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169 MachineOptimizationRemarkEmitter &MORE,

170 MachineOptimizationRemarkMissed &R);

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181LLVM_ABI std::optional<int64_t>

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186 const MachineRegisterInfo &MRI);

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197LLVM_ABI std::optional

200 bool LookThroughInstrs = true);

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206 bool LookThroughInstrs = true, bool LookThroughAnyExt = false);

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215LLVM_ABI std::optional

218 bool LookThroughInstrs = true);

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300 const MachineRegisterInfo &MRI);

301LLVM_ABI std::optional

303 const MachineRegisterInfo &MRI);

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309 const MachineRegisterInfo &MRI);

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313 const MachineRegisterInfo &MRI);

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318 const MachineRegisterInfo &MRI);

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320LLVM_ABI std::optional

322 const MachineRegisterInfo &MRI);

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327LLVM_ABI std::optional<SmallVector>

329 std::function<unsigned(APInt)> CB);

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331LLVM_ABI std::optional<SmallVector>

333 unsigned DstScalarSizeInBits, unsigned ExtOp,

334 const MachineRegisterInfo &MRI);

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341 GISelValueTracking *ValueTracking = nullptr);

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346 bool SNaN = false);

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354 const MachinePointerInfo &MPO);

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363 MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg,

364 const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy = LLT());

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378 LLT

379 getCoverTy(LLT OrigTy, LLT TargetTy);

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405 int64_t Cst;

407 bool IsReg;

408

409public:

412 bool isReg() const { return IsReg; }

413 bool isCst() const { return !IsReg; }

415 assert(isReg() && "Expected a register!");

416 return Reg;

417 }

419 assert(isCst() && "Expected a constant!");

420 return Cst;

421 }

422};

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438LLVM_ABI std::optional<int64_t>

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443LLVM_ABI std::optional<int64_t>

445 const MachineRegisterInfo &MRI);

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449LLVM_ABI std::optional

451 bool AllowUndef = true);

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456 const MachineRegisterInfo &MRI,

457 int64_t SplatValue, bool AllowUndef);

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462 const MachineRegisterInfo &MRI,

463 const APInt &SplatValue,

464 bool AllowUndef);

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469 const MachineRegisterInfo &MRI,

470 int64_t SplatValue, bool AllowUndef);

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475 const MachineRegisterInfo &MRI,

476 const APInt &SplatValue,

477 bool AllowUndef);

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482 const MachineRegisterInfo &MRI,

483 bool AllowUndef = false);

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488 const MachineRegisterInfo &MRI,

489 bool AllowUndef = false);

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498 const MachineRegisterInfo &MRI,

499 bool AllowFP = true,

500 bool AllowOpaqueConstants = true);

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507 const MachineRegisterInfo &MRI,

508 bool AllowUndefs = false);

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513 const MachineRegisterInfo &MRI,

514 bool AllowUndefs = false);

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541 const MachineRegisterInfo &MRI);

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548 const MachineRegisterInfo &MRI);

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553LLVM_ABI std::optional

555 const MachineRegisterInfo &MRI);

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562 std::function<bool(const Constant *ConstVal)> Match,

563 bool AllowUndefs = false);

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568 bool IsVector, bool IsFP);

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572 bool IsVector, bool IsFP);

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577 bool IsFP);

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606 bool ConsiderFlagsAndMetadata = true);

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610 bool ConsiderFlagsAndMetadata = true);

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615 unsigned Depth = 0);

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620 unsigned Depth = 0);

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625 unsigned Depth = 0);

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654 GIConstantKind Kind;

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662 : Kind(Kind), Value(Value) {};

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670 LLVM_ABI static std::optional

672};

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696 GFConstantKind Kind;

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703 Values.push_back(Value);

704 }

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709 const_iterator begin() const {

711 "Expected fixed vector or scalar constant");

712 return Values.begin();

713 }

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715 const_iterator end() const {

717 "Expected fixed vector or scalar constant");

718 return Values.end();

719 }

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723 return Values.size();

724 }

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729 LLVM_ABI static std::optional

731};

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733}

734#endif

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file declares a class to represent arbitrary precision floating point values and provide a varie...

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Implement a low-level type suitable for MachineInstr level instruction selection.

Promote Memory to Register

MachineInstr unsigned OpIdx

uint64_t IntrinsicInst * II

static const char PassName[]

Class for arbitrary precision integers.

Represent the analysis usage information of a pass.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...

ConstantFP - Floating Point Values [float, double].

GFConstantKind

Definition Utils.h:693

@ FixedVector

Definition Utils.h:693

@ ScalableVector

Definition Utils.h:693

@ Scalar

Definition Utils.h:693

const_iterator begin() const

Definition Utils.h:709

static LLVM_ABI std::optional< GFConstant > getConstant(Register Const, const MachineRegisterInfo &MRI)

GFConstant(const APFloat &Value, GFConstantKind Kind)

Definition Utils.h:702

GFConstant(ArrayRef< APFloat > Values)

Definition Utils.h:700

GFConstantKind getKind() const

Returns the kind of of this constant, e.g, Scalar.

Definition Utils.h:707

LLVM_ABI APFloat getScalarValue() const

Returns the value, if this constant is a scalar.

const_iterator end() const

Definition Utils.h:715

size_t size() const

Definition Utils.h:721

LLVM_ABI APInt getScalarValue() const

Returns the value, if this constant is a scalar.

GIConstant(const APInt &Value, GIConstantKind Kind)

Definition Utils.h:661

static LLVM_ABI std::optional< GIConstant > getConstant(Register Const, const MachineRegisterInfo &MRI)

GIConstantKind getKind() const

Returns the kind of of this constant, e.g, Scalar.

Definition Utils.h:665

GIConstantKind

Definition Utils.h:651

@ FixedVector

Definition Utils.h:651

@ ScalableVector

Definition Utils.h:651

@ Scalar

Definition Utils.h:651

GIConstant(ArrayRef< APInt > Values)

Definition Utils.h:659

This is an important class for using LLVM in a threaded context.

Describe properties that are true of each instruction in the target description file.

Helper class to build MachineInstr.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Analysis providing profile information.

RegOrConstant(Register Reg)

Definition Utils.h:410

Definition Utils.h:414

bool isCst() const

Definition Utils.h:413

int64_t getCst() const

Definition Utils.h:418

RegOrConstant(int64_t Cst)

Definition Utils.h:411

bool isReg() const

Definition Utils.h:412

Holds all the information related to register banks.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

Target-Independent Code Generator Pass Configuration Options.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

@ C

The default llvm calling convention, compatible with C.

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())

Return a virtual register corresponding to the incoming argument register PhysReg.

LLVM_ABI std::optional< SmallVector< APInt > > ConstantFoldICmp(unsigned Pred, const Register Op1, const Register Op2, unsigned DstScalarSizeInBits, unsigned ExtOp, const MachineRegisterInfo &MRI)

LLVM_ABI bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)

Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...

LLVM_ABI Type * getTypeForLLT(LLT Ty, LLVMContext &C)

Get the type back from LLT.

LLVM_ABI Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)

Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...

LLVM_ABI MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)

See if Reg is defined by an single def instruction that is Opcode.

LLVM_ABI const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)

LLVM_ABI bool canCreatePoison(const Operator *Op, bool ConsiderFlagsAndMetadata=true)

LLVM_ABI std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)

If VReg is defined by a G_CONSTANT, return the corresponding value.

LLVM_ABI std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)

LLVM_ABI std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)

LLVM_ABI bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)

Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...

LLVM_ABI std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)

LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)

Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...

LLVM_ABI bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)

Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...

LLVM_ABI std::optional< SmallVector< unsigned > > ConstantFoldCountZeros(Register Src, const MachineRegisterInfo &MRI, std::function< unsigned(APInt)> CB)

Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on Src.

LLVM_ABI std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)

LLVM_ABI std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)

GISelWorkList< 4 > SmallInstListTy

Definition Utils.h:579

LLVM_ABI std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)

Determines if MI defines a constant integer or a splat vector of constant integers.

LLVM_ABI bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)

Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...

LLVM_ABI MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)

Find the def instruction for Reg, folding away any trivial copies.

LLVM_ABI bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)

Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...

LLVM_ABI void reportGISelWarning(MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)

Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.

LLVM_ABI bool isGuaranteedNotToBeUndef(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)

Returns true if V cannot be undef, but may be poison.

LLVM_ABI bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)

Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...

LLVM_ABI LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)

Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...

LLVM_ABI std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)

If VReg is defined by a G_CONSTANT fits in int64_t returns it.

LLVM_ABI std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)

auto dyn_cast_or_null(const Y &Val)

LLVM_ABI const APInt & getIConstantFromReg(Register VReg, const MachineRegisterInfo &MRI)

VReg is defined by a G_CONSTANT, return the corresponding value.

LLVM_ABI bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)

Return true if the specified instruction is known to be a constant, or a vector of constants.

LLVM_ABI bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)

Check if DstReg can be replaced with SrcReg depending on the register constraints.

LLVM_ABI void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)

LLVM_ABI void reportGISelFailure(MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)

Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.

LLVM_ABI std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)

If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...

LLVM_ABI bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)

Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...

LLVM_ABI bool canCreateUndefOrPoison(const Operator *Op, bool ConsiderFlagsAndMetadata=true)

canCreateUndefOrPoison returns true if Op can create undef or poison from non-undef & non-poison oper...

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

LLVM_ABI SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)

Tries to constant fold a vector binop with sources Op1 and Op2.

LLVM_ABI std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)

Returns a floating point scalar constant of a build vector splat if it exists.

LLVM_ABI std::optional< APInt > ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)

LLVM_ABI void extractParts(Register Reg, LLT Ty, int NumParts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)

Helper function to split a wide generic register into bitwise blocks with the given Type (which impli...

LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)

Modify analysis usage so it preserves passes required for the SelectionDAG fallback.

LLVM_ABI LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)

Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.

LLVM_ABI unsigned getInverseGMinMaxOpcode(unsigned MinMaxOpc)

Returns the inverse opcode of MinMaxOpc, which is a generic min/max opcode like G_SMIN.

LLVM_ABI bool isGuaranteedNotToBeUndefOrPoison(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)

Return true if this function can prove that V does not have undef bits and is never poison.

LLVM_ABI std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)

If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...

LLVM_ABI bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)

LLVM_ABI std::optional< APFloat > isConstantOrConstantSplatVectorFP(MachineInstr &MI, const MachineRegisterInfo &MRI)

Determines if MI defines a float constant integer or a splat vector of float constant integers.

LLVM_ABI APFloat getAPFloatFromSize(double Val, unsigned Size)

Returns an APFloat from Val converted to the appropriate size.

LLVM_ABI bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)

Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...

LLVM_ABI void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)

LLVM_ABI Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)

Try to constrain Reg to the specified register class.

LLVM_ABI int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)

Returns an integer representing true, as defined by the TargetBooleanContents.

LLVM_ABI bool isKnownNeverNaN(const Value *V, const SimplifyQuery &SQ, unsigned Depth=0)

Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...

LLVM_ABI std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)

If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...

LLVM_ABI bool isPreISelGenericFloatingPointOpcode(unsigned Opc)

Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...

bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)

Returns true if Val can be assumed to never be a signaling NaN.

Definition Utils.h:349

LLVM_ABI std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)

Find the def instruction for Reg, and underlying value Register folding away any copies.

LLVM_ABI void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)

LLVM_ABI bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true, unsigned Depth=0)

Return true if the given value is known to have exactly one bit set when defined.

LLVM_ABI Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)

Find the source register for Reg, folding away any trivial copies.

LLVM_ABI LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)

Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.

LLVM_ABI bool isGuaranteedNotToBePoison(const Value *V, AssumptionCache *AC=nullptr, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, unsigned Depth=0)

Returns true if V cannot be poison, but may be undef.

LLVM_ABI std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)

LLVM_ABI bool isAssertMI(const MachineInstr &MI)

Returns true if the instruction MI is one of the assert instructions.

LLVM_ABI void extractVectorParts(Register Reg, unsigned NumElts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)

Version which handles irregular sub-vector splits.

LLVM_ABI int getSplatIndex(ArrayRef< int > Mask)

If all non-negative Mask elements are the same value, return that value.

LLVM_ABI bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)

Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...

LLVM_ABI Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)

Simple struct used to hold a Register value and the instruction which defines it.

Definition Utils.h:231

Definition Utils.h:233

MachineInstr * MI

Definition Utils.h:232

Definition Utils.h:210

APFloat Value

Definition Utils.h:209

This class contains a discriminated union of information about pointers in memory operands,...

Simple struct used to hold a constant integer value and a virtual register.

Definition Utils.h:190

APInt Value

Definition Utils.h:191

Definition Utils.h:192