CombinerHelper.h Source File (original) (raw)

17#ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H

18#define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H

27#include

29namespace llvm {

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234 std::tuple<Register, unsigned> &MatchInfo) const;

236 std::tuple<Register, unsigned> &MatchInfo) const;

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373 unsigned &ShiftVal) const;

375 const unsigned &ShiftVal) const;

377 unsigned TargetShiftAmount) const;

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417 bool

419 std::pair<Register, bool> &PtrRegAndCommute) const;

420 void

422 std::pair<Register, bool> &PtrRegAndCommute) const;

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441 bool

443 std::pair<MachineInstr *, LLT> &MatchInfo) const;

444 void

446 std::pair<MachineInstr *, LLT> &MatchInfo) const;

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529 unsigned OpIdx) const;

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536 std::tuple<Register, Register> &MatchInfo) const;

538 std::tuple<Register, Register> &MatchInfo) const;

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550 std::tuple<Register, int64_t> &MatchInfo) const;

552 std::tuple<Register, int64_t> &MatchInfo) const;

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586 std::pair<Register, Register> &MatchInfo) const;

588 std::pair<Register, Register> &MatchInfo) const;

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604 const unsigned &SelectOpNo) const;

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631 SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo) const;

634 SmallVectorImpl<std::pair<Register, MachineInstr *>> &MatchInfo) const;

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662 int64_t &MatchInfo) const;

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804 bool CanReassociate = false) const;

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825 bool

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894 std::optional<int64_t> &MatchInfo) const;

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1049private:

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1051 bool isIndexedLoadStoreLegal(GLoadStore &LdSt) const;

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1072 std::optional<SmallVector<Register, 8>>

1073 findCandidatesForLoadOrCombine(const MachineInstr *Root) const;

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1086 std::optional<std::tuple<GZExtLoad *, int64_t, GZExtLoad *>>

1087 findLoadOffsetsForLoadOrCombine(

1090 const unsigned MemSizeInBits) const;

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1095 bool reassociationCanBreakAddressingModePattern(MachineInstr &PtrAdd) const;

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1099 enum class SelectPatternNaNBehaviour {

1100 NOT_APPLICABLE = 0,

1101 RETURNS_NAN,

1102 RETURNS_OTHER,

1103 RETURNS_ANY

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1105 };

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1112 SelectPatternNaNBehaviour

1114 bool IsOrderedComparison) const;

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1129 SelectPatternNaNBehaviour VsNaNRetVal) const;

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1147 bool isConstantSplatVector(Register Src, int64_t SplatValue,

1148 bool AllowUndefs) const;

1149 bool isConstantOrConstantVectorI(Register Src) const;

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1151 std::optional getConstantOrConstantSplatVector(Register Src) const;

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1156 bool tryFoldAndOrOrICmpsUsingRanges(GLogicalBinOp *Logic,

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1162 bool isCastFree(unsigned Opcode, LLT ToTy, LLT FromTy) const;

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1164 bool constantFoldICmp(const GICmp &ICmp, const GIConstant &LHSCst,

1166 bool constantFoldFCmp(const GFCmp &FCmp, const GFConstant &LHSCst,

1168};

1169}

1170

1171#endif

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

AMDGPU Register Bank Select

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Analysis containing CSE Info

This file defines the DenseMap class.

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Implement a low-level type suitable for MachineInstr level instruction selection.

MachineInstr unsigned OpIdx

const SmallVectorImpl< MachineOperand > & Cond

This file defines the SmallVector class.

Class for arbitrary precision integers.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo) const

bool matchCommuteShift(MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchRepeatedFPDivisor(MachineInstr &MI, SmallVector< MachineInstr * > &MatchInfo) const

bool matchFoldC2MinusAPlusC1(const MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchLoadOrCombine(MachineInstr &MI, BuildFnTy &MatchInfo) const

Match expression trees of the form.

bool tryCombine(MachineInstr &MI) const

Try to transform MI by using all of the above combine functions.

const RegisterBank * getRegBank(Register Reg) const

Get the register bank of Reg.

void applyPtrAddZero(MachineInstr &MI) const

bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2) const

Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions.

void applyUDivOrURemByConst(MachineInstr &MI) const

bool matchConstantFoldBinOp(MachineInstr &MI, APInt &MatchInfo) const

Do constant folding when opportunities are exposed after MIR building.

void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) const

bool matchUnmergeValuesAnyExtBuildVector(const MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchSelectSameVal(MachineInstr &MI) const

Optimize (cond ? x : x) -> x.

bool matchAddEToAddO(MachineInstr &MI, BuildFnTy &MatchInfo) const

Match: (G_*ADDE x, y, 0) -> (G_*ADDO x, y) (G_*SUBE x, y, 0) -> (G_*SUBO x, y)

bool matchReassocConstantInnerRHS(GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo) const

bool matchBitfieldExtractFromShr(MachineInstr &MI, BuildFnTy &MatchInfo) const

Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width.

bool matchFoldAMinusC1PlusC2(const MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchTruncSSatU(MachineInstr &MI, Register &MatchInfo) const

void applySimplifyURemByPow2(MachineInstr &MI) const

Combine G_UREM x, (known power of 2) to an add and bitmasking.

bool matchCombineUnmergeZExtToZExt(MachineInstr &MI) const

Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.

bool matchPtrAddZero(MachineInstr &MI) const

}

void applyCombineConcatVectors(MachineInstr &MI, SmallVector< Register > &Ops) const

Replace MI with a flattened build_vector with Ops or an implicit_def if Ops is empty.

void applyXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo) const

bool canCombineFMadOrFMA(MachineInstr &MI, bool &AllowFusionGlobally, bool &HasFMAD, bool &Aggressive, bool CanReassociate=false) const

bool matchFoldAPlusC1MinusC2(const MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchExtractVecEltBuildVec(MachineInstr &MI, Register &Reg) const

void applyCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts) const

bool matchShiftsTooBig(MachineInstr &MI, std::optional< int64_t > &MatchInfo) const

Match shifts greater or equal to the range (the bitwidth of the result datatype, or the effective bit...

bool matchCombineFAddFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (fadd (fpext (fmul x,...

bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo) const

void applyCombineShuffleConcat(MachineInstr &MI, SmallVector< Register > &Ops) const

Replace MI with a flattened build_vector with Ops or an implicit_def if Ops is empty.

void replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement) const

Delete MI and replace all of its uses with Replacement.

void applyCombineShuffleToBuildVector(MachineInstr &MI) const

Replace MI with a build_vector.

bool matchZextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Combine zext of trunc.

bool matchCombineExtractedVectorLoad(MachineInstr &MI, BuildFnTy &MatchInfo) const

Combine a G_EXTRACT_VECTOR_ELT of a load into a narrowed load.

void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const

MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.

void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const

Replace a single register operand with a new register and inform the observer of the changes.

bool matchReassocCommBinOp(MachineInstr &MI, BuildFnTy &MatchInfo) const

Reassociate commutative binary operations like G_ADD.

bool matchExtractVectorElementWithBuildVectorTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Combine extract vector element with a build vector trunc on the vector register.

void applyBuildFnMO(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Use a function which takes in a MachineIRBuilder to perform a combine.

bool matchCommuteConstantToRHS(MachineInstr &MI) const

Match constant LHS ops that should be commuted.

const DataLayout & getDataLayout() const

bool matchBinOpSameVal(MachineInstr &MI) const

Optimize (x op x) -> x.

bool matchSimplifyNegMinMax(MachineInstr &MI, BuildFnTy &MatchInfo) const

Tranform (neg (min/max x, (neg x))) into (max/min x, (neg x)).

bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI) const

Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are iden...

bool matchNonNegZext(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Combine zext nneg to sext.

void applyUMulHToLShr(MachineInstr &MI) const

void applyNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate) const

bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo) const

Fold (shift (shift base, x), y) -> (shift base (x+y))

void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg) const

bool matchTruncLshrBuildVectorFold(MachineInstr &MI, Register &MatchInfo) const

bool matchAllExplicitUsesAreUndef(MachineInstr &MI) const

Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF.

bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI) const

Returns true if DefMI precedes UseMI or they are the same instruction.

bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo) const

bool matchTruncSSatS(MachineInstr &MI, Register &MatchInfo) const

const TargetLowering & getTargetLowering() const

bool matchExtractVectorElementWithDifferentIndices(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Combine extract vector element with a insert vector element on the vector register and different indi...

bool matchShuffleUndefRHS(MachineInstr &MI, BuildFnTy &MatchInfo) const

Remove references to rhs if it is undef.

void applyBuildInstructionSteps(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo) const

Replace MI with a series of instructions described in MatchInfo.

void applySDivByPow2(MachineInstr &MI) const

void applySimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo) const

void applyUDivByPow2(MachineInstr &MI) const

Given an G_UDIV MI expressing an unsigned divided by a pow2 constant, return expressions that impleme...

bool matchOr(MachineInstr &MI, BuildFnTy &MatchInfo) const

Combine ors.

bool matchLshrOfTruncOfLshr(MachineInstr &MI, LshrOfTruncOfLshr &MatchInfo, MachineInstr &ShiftMI) const

Fold (lshr (trunc (lshr x, C1)), C2) -> trunc (shift x, (C1 + C2))

bool matchInsertVectorElementOOB(MachineInstr &MI, BuildFnTy &MatchInfo) const

Combine insert vector element OOB.

bool matchSimplifyAddToSub(MachineInstr &MI, std::tuple< Register, Register > &MatchInfo) const

Return true if MI is a G_ADD which can be simplified to a G_SUB.

void replaceInstWithConstant(MachineInstr &MI, int64_t C) const

Replace an instruction with a G_CONSTANT with value C.

bool tryEmitMemcpyInline(MachineInstr &MI) const

Emit loads and stores that perform the given memcpy.

bool matchCombineFSubFpExtFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (fsub (fpext (fmul x,...

void applyFsubToFneg(MachineInstr &MI, Register &MatchInfo) const

bool matchConstantLargerBitWidth(MachineInstr &MI, unsigned ConstIdx) const

Checks if constant at ConstIdx is larger than MI 's bitwidth.

GISelValueTracking * getValueTracking() const

Definition CombinerHelper.h:132

void applyCombineCopy(MachineInstr &MI) const

bool matchExtractVectorElement(MachineInstr &MI, BuildFnTy &MatchInfo) const

Combine extract vector element.

bool matchSextOfTrunc(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Combine sext of trunc.

bool matchAddSubSameReg(MachineInstr &MI, Register &Src) const

Transform G_ADD(x, G_SUB(y, x)) to y.

bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData) const

bool matchMergeXAndZero(const MachineInstr &MI, BuildFnTy &MatchInfo) const

void applyCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute) const

bool matchCombineFSubFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (fsub (fmul x, y), z) -> (fmad x,...

bool matchCombineFAddFMAFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (fadd (fmad x,...

bool matchSextTruncSextLoad(MachineInstr &MI) const

bool matchMulOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const

bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo) const

Fold away a merge of an unmerge of the corresponding values.

bool matchCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo) const

bool matchCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI, Register &UnmergeSrc) const

bool matchDivByPow2(MachineInstr &MI, bool IsSigned) const

Given an G_SDIV MI expressing a signed divided by a pow2 constant, return expressions that implements...

bool matchAddOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const

bool matchNarrowBinopFeedingAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchShlOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const

bool matchRedundantNegOperands(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform (fadd x, fneg(y)) -> (fsub x, y) (fadd fneg(x), y) -> (fsub y, x) (fsub x,...

bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo) const

Match (and (load x), mask) -> zextload x.

bool matchCombineFAddFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform (fadd (fmul x, y), z) -> (fma x, y, z) (fadd (fmul x, y), z) -> (fmad x,...

bool matchCombineCopy(MachineInstr &MI) const

bool matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI) const

void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo) const

bool matchXorOfAndWithSameReg(MachineInstr &MI, std::pair< Register, Register > &MatchInfo) const

Fold (xor (and x, y), y) -> (and (not x), y) {.

bool matchCombineShuffleVector(MachineInstr &MI, SmallVectorImpl< Register > &Ops) const

Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors.

void applyCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst) const

bool matchTruncateOfExt(const MachineInstr &Root, const MachineInstr &ExtMI, BuildFnTy &MatchInfo) const

Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).

bool matchCombineAddP2IToPtrAdd(MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute) const

Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y,...

void replaceInstWithFConstant(MachineInstr &MI, double C) const

Replace an instruction with a G_FCONSTANT with value C.

bool matchMergeXAndUndef(const MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchFunnelShiftToRotate(MachineInstr &MI) const

Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.

bool matchOrShiftToFunnelShift(MachineInstr &MI, bool AllowScalarConstants, BuildFnTy &MatchInfo) const

bool matchRedundantSExtInReg(MachineInstr &MI) const

void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const

Replace the opcode in instruction with a new opcode and inform the observer of the changes.

void applyFunnelShiftConstantModulo(MachineInstr &MI) const

Replaces the shift amount in MI with ShiftAmt % BW.

bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx) const

Check if operand OpIdx is zero.

bool matchFoldC1Minus2MinusC2(const MachineInstr &MI, BuildFnTy &MatchInfo) const

void applyCombineShlOfExtend(MachineInstr &MI, const RegisterImmPair &MatchData) const

void applyUseVectorTruncate(MachineInstr &MI, Register &MatchInfo) const

CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B, bool IsPreLegalize, GISelValueTracking *VT=nullptr, MachineDominatorTree *MDT=nullptr, const LegalizerInfo *LI=nullptr)

bool matchShuffleDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo) const

Turn shuffle a, b, mask -> shuffle undef, b, mask iff mask does not reference a.

bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const

Transform a multiply by a power-of-2 value to a left shift.

void applyCombineShuffleVector(MachineInstr &MI, ArrayRef< Register > Ops) const

Replace MI with a concat_vectors with Ops.

bool matchCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst) const

bool matchCombineUnmergeUndef(MachineInstr &MI, std::function< void(MachineIRBuilder &)> &MatchInfo) const

Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...

void applyFoldBinOpIntoSelect(MachineInstr &MI, const unsigned &SelectOpNo) const

SelectOperand is the operand in binary operator MI that is the select to fold.

bool matchFoldAMinusC1MinusC2(const MachineInstr &MI, BuildFnTy &MatchInfo) const

void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo) const

bool matchMulOBy2(MachineInstr &MI, BuildFnTy &MatchInfo) const

Match: (G_UMULO x, 2) -> (G_UADDO x, x) (G_SMULO x, 2) -> (G_SADDO x, x)

bool matchCombineShuffleConcat(MachineInstr &MI, SmallVector< Register > &Ops) const

void applySextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo) const

bool tryCombineCopy(MachineInstr &MI) const

If MI is COPY, try to combine it.

bool matchTruncUSatU(MachineInstr &MI, MachineInstr &MinMI) const

bool matchICmpToLHSKnownBits(MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchExtOfExt(const MachineInstr &FirstMI, const MachineInstr &SecondMI, BuildFnTy &MatchInfo) const

bool IsPreLegalize

Definition CombinerHelper.h:121

bool matchReassocPtrAdd(MachineInstr &MI, BuildFnTy &MatchInfo) const

Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage.

bool matchCanonicalizeFCmp(const MachineInstr &MI, BuildFnTy &MatchInfo) const

bool isPreLegalize() const

bool matchUndefShuffleVectorMask(MachineInstr &MI) const

Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask.

bool matchAnyExplicitUseIsUndef(MachineInstr &MI) const

Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF.

bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg) const

Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.

bool matchCombineSubToAdd(MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo) const

If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with...

bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx) const

Check if operand OpIdx is known to be a power of 2.

bool matchCombineConcatVectors(MachineInstr &MI, SmallVector< Register > &Ops) const

If MI is G_CONCAT_VECTORS, try to combine it.

bool matchInsertExtractVecEltOutOfBounds(MachineInstr &MI) const

Return true if a G_{EXTRACT,INSERT}_VECTOR_ELT has an out of range index.

bool matchExtractVectorElementWithShuffleVector(const MachineInstr &MI, const MachineInstr &MI2, BuildFnTy &MatchInfo) const

Combine extract vector element with a shuffle vector on the vector register.

bool matchExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * > > &MatchInfo) const

LLVMContext & getContext() const

void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo) const

bool isConstantLegalOrBeforeLegalizer(const LLT Ty) const

bool matchNotCmp(MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate) const

Combine inverting a result of a compare into the opposite cond code.

bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo) const

Match sext_inreg(load p), imm -> sextload p.

bool matchSelectIMinMax(const MachineOperand &MO, BuildFnTy &MatchInfo) const

Combine select to integer min/max.

void applyCombineConstantFoldFpUnary(MachineInstr &MI, const ConstantFP *Cst) const

Transform fp_instr(cst) to constant result of the fp operation.

bool isLegal(const LegalityQuery &Query) const

bool matchICmpToTrueFalseKnownBits(MachineInstr &MI, int64_t &MatchInfo) const

bool tryReassocBinOp(unsigned Opc, Register DstReg, Register Op0, Register Op1, BuildFnTy &MatchInfo) const

Try to reassociate to reassociate operands of a commutative binop.

void eraseInst(MachineInstr &MI) const

Erase MI.

bool matchConstantFoldFPBinOp(MachineInstr &MI, ConstantFP *&MatchInfo) const

Do constant FP folding when opportunities are exposed after MIR building.

void applyBuildFnNoErase(MachineInstr &MI, BuildFnTy &MatchInfo) const

Use a function which takes in a MachineIRBuilder to perform a combine.

bool matchUseVectorTruncate(MachineInstr &MI, Register &MatchInfo) const

bool matchUndefStore(MachineInstr &MI) const

Return true if a G_STORE instruction MI is storing an undef value.

MachineRegisterInfo & MRI

Definition CombinerHelper.h:117

void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg) const

Transform PtrToInt(IntToPtr(x)) to x.

void applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI) const

bool matchConstantFPOp(const MachineOperand &MOP, double C) const

Return true if MOP is defined by a G_FCONSTANT or splat with a value exactly equal to C.

MachineInstr * buildUDivOrURemUsingMul(MachineInstr &MI) const

Given an G_UDIV MI or G_UREM MI expressing a divide by constant, return an expression that implements...

void applyExtractVecEltBuildVec(MachineInstr &MI, Register &Reg) const

bool matchFoldBinOpIntoSelect(MachineInstr &MI, unsigned &SelectOpNo) const

Push a binary operator through a select on constants.

bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount) const

bool tryCombineExtendingLoads(MachineInstr &MI) const

If MI is extend that consumes the result of a load, try to combine it.

bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const

bool matchBuildVectorIdentityFold(MachineInstr &MI, Register &MatchInfo) const

bool matchBitfieldExtractFromShrAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const

Match: shr (and x, n), k -> ubfx x, pos, width.

void applyTruncSSatS(MachineInstr &MI, Register &MatchInfo) const

bool matchConstantFoldCastOp(MachineInstr &MI, APInt &MatchInfo) const

Do constant folding when opportunities are exposed after MIR building.

bool tryCombineShuffleVector(MachineInstr &MI) const

Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.

void applyRotateOutOfRange(MachineInstr &MI) const

bool matchReassocFoldConstantsInSubTree(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo) const

bool matchHoistLogicOpWithSameOpcodeHands(MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo) const

Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))

bool matchBitfieldExtractFromAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const

Match: and (lshr x, cst), mask -> ubfx x, cst, width.

bool matchBitfieldExtractFromSExtInReg(MachineInstr &MI, BuildFnTy &MatchInfo) const

Form a G_SBFX from a G_SEXT_INREG fed by a right shift.

bool matchNarrowBinop(const MachineInstr &TruncMI, const MachineInstr &BinopMI, BuildFnTy &MatchInfo) const

trunc (binop X, C) --> binop (trunc X, trunc C).

bool matchUndefSelectCmp(MachineInstr &MI) const

Return true if a G_SELECT instruction MI has an undef comparison.

bool matchAndOrDisjointMask(MachineInstr &MI, BuildFnTy &MatchInfo) const

void replaceInstWithUndef(MachineInstr &MI) const

Replace an instruction with a G_IMPLICIT_DEF.

bool matchRedundantBinOpInEquality(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform: (X + Y) == X -> Y == 0 (X - Y) == X -> Y == 0 (X ^ Y) == X -> Y == 0 (X + Y) !...

bool matchOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond) const

If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping o...

bool matchAddOverflow(MachineInstr &MI, BuildFnTy &MatchInfo) const

Combine addos.

void applyAshShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo) const

bool matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo) const

Combine selects.

bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo) const

bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) const

Transform X, Y = G_UNMERGE Z -> X = G_TRUNC Z.

bool matchFsubToFneg(MachineInstr &MI, Register &MatchInfo) const

bool matchRotateOutOfRange(MachineInstr &MI) const

void applyExpandFPowI(MachineInstr &MI, int64_t Exponent) const

Expands FPOWI into a series of multiplications and a division if the exponent is negative.

void setRegBank(Register Reg, const RegisterBank *RegBank) const

Set the register bank of Reg.

bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx) const

Return true if a G_SELECT instruction MI has a constant comparison.

bool matchCommuteFPConstantToRHS(MachineInstr &MI) const

Match constant LHS FP ops that should be commuted.

void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI) const

bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info) const

bool matchRedundantOr(MachineInstr &MI, Register &Replacement) const

void applyTruncSSatU(MachineInstr &MI, Register &MatchInfo) const

bool matchCombineFSubFpExtFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y),...

bool matchTruncBuildVectorFold(MachineInstr &MI, Register &MatchInfo) const

bool matchSubOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo) const

void applyCombineTruncOfShift(MachineInstr &MI, std::pair< MachineInstr *, LLT > &MatchInfo) const

bool matchConstantOp(const MachineOperand &MOP, int64_t C) const

Return true if MOP is defined by a G_CONSTANT or splat with a value equal to C.

const LegalizerInfo * LI

Definition CombinerHelper.h:122

void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const

void applyCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, Register &UnmergeSrc) const

bool matchUMulHToLShr(MachineInstr &MI) const

MachineDominatorTree * MDT

Definition CombinerHelper.h:120

MachineIRBuilder & getBuilder() const

Definition CombinerHelper.h:134

void applyFunnelShiftToRotate(MachineInstr &MI) const

bool matchSimplifySelectToMinMax(MachineInstr &MI, BuildFnTy &MatchInfo) const

void applyRepeatedFPDivisor(SmallVector< MachineInstr * > &MatchInfo) const

bool matchTruncUSatUToFPTOUISat(MachineInstr &MI, MachineInstr &SrcMI) const

const RegisterBankInfo * RBI

Definition CombinerHelper.h:123

bool matchMulOBy0(MachineInstr &MI, BuildFnTy &MatchInfo) const

Match: (G_*MULO x, 0) -> 0 + no carry out.

GISelValueTracking * VT

Definition CombinerHelper.h:119

bool matchCombineUnmergeConstant(MachineInstr &MI, SmallVectorImpl< APInt > &Csts) const

Transform G_UNMERGE Constant -> Constant1, Constant2, ...

void applyShiftOfShiftedLogic(MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo) const

const TargetRegisterInfo * TRI

Definition CombinerHelper.h:124

bool matchRedundantAnd(MachineInstr &MI, Register &Replacement) const

bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI) const

Returns true if DefMI dominates UseMI.

GISelChangeObserver & Observer

Definition CombinerHelper.h:118

void applyBuildFn(MachineInstr &MI, BuildFnTy &MatchInfo) const

Use a function which takes in a MachineIRBuilder to perform a combine.

bool matchCombineTruncOfShift(MachineInstr &MI, std::pair< MachineInstr *, LLT > &MatchInfo) const

Transform trunc (shl x, K) to shl (trunc x), K if K < VT.getScalarSizeInBits().

bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal) const

Reduce a shift by a constant to an unmerge and a shift on a half sized type.

bool matchUDivOrURemByConst(MachineInstr &MI) const

Combine G_UDIV or G_UREM by constant into a multiply by magic constant.

bool matchAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const

Combine ands.

bool matchSuboCarryOut(const MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchRedundantSextInReg(MachineInstr &Root, MachineInstr &Other, BuildFnTy &MatchInfo) const

bool matchConstantFoldFMA(MachineInstr &MI, ConstantFP *&MatchInfo) const

Constant fold G_FMA/G_FMAD.

bool matchCombineFSubFNegFMulToFMadOrFMA(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (fsub (fneg (fmul,...

bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg) const

Transform zext(trunc(x)) to x.

bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx) const

Check if operand OpIdx is undef.

void applyLshrOfTruncOfLshr(MachineInstr &MI, LshrOfTruncOfLshr &MatchInfo) const

bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen=0) const

Optimize memcpy intrinsics et al, e.g.

bool matchFreezeOfSingleMaybePoisonOperand(MachineInstr &MI, BuildFnTy &MatchInfo) const

void applySDivOrSRemByConst(MachineInstr &MI) const

MachineInstr * buildSDivOrSRemUsingMul(MachineInstr &MI) const

Given an G_SDIV MI or G_SREM MI expressing a signed divide by constant, return an expression that imp...

bool isLegalOrHasWidenScalar(const LegalityQuery &Query) const

bool matchCanonicalizeICmp(const MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchCastOfBuildVector(const MachineInstr &CastMI, const MachineInstr &BVMI, BuildFnTy &MatchInfo) const

bool matchSubAddSameReg(MachineInstr &MI, BuildFnTy &MatchInfo) const

Transform: (x + y) - y -> x (x + y) - x -> y x - (y + x) -> 0 - y x - (x + z) -> 0 - z.

bool matchReassocConstantInnerLHS(GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo) const

bool matchCastOfInteger(const MachineInstr &CastMI, APInt &MatchInfo) const

bool matchOverlappingAnd(MachineInstr &MI, BuildFnTy &MatchInfo) const

Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0.

bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) const

Transform anyext(trunc(x)) to x.

void applyExtractAllEltsFromBuildVector(MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * > > &MatchInfo) const

MachineIRBuilder & Builder

Definition CombinerHelper.h:116

void applyCommuteBinOpOperands(MachineInstr &MI) const

void replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx) const

Delete MI and replace all of its uses with its OpIdx-th operand.

void applySextTruncSextLoad(MachineInstr &MI) const

const MachineFunction & getMachineFunction() const

bool matchCombineFAddFpExtFMulToFMadOrFMAAggressive(MachineInstr &MI, BuildFnTy &MatchInfo) const

bool matchExtractVectorElementWithBuildVector(const MachineInstr &MI, const MachineInstr &MI2, BuildFnTy &MatchInfo) const

Combine extract vector element with a build vector on the vector register.

bool matchSDivOrSRemByConst(MachineInstr &MI) const

Combine G_SDIV or G_SREM by constant into a multiply by magic constant.

void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond) const

void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal) const

bool matchCastOfSelect(const MachineInstr &Cast, const MachineInstr &SelectMI, BuildFnTy &MatchInfo) const

bool matchFPowIExpansion(MachineInstr &MI, int64_t Exponent) const

Match FPOWI if it's safe to extend it into a series of multiplications.

void applyCombineInsertVecElts(MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo) const

bool matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands) const

Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.

void applyCombineUnmergeMergeToPlainValues(MachineInstr &MI, SmallVectorImpl< Register > &Operands) const

bool matchAshrShlToSextInreg(MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo) const

Match ashr (shl x, C), C -> sext_inreg (C)

void applyCombineUnmergeZExtToZExt(MachineInstr &MI) const

ConstantFP - Floating Point Values [float, double].

A parsed version of the target data layout string in and methods for querying it.

An floating-point-like constant.

An integer-like constant.

Abstract class that contains various methods for clients to notify about changes.

Represents any type of generic load or store.

Represents a logical binary operation.

This is an important class for using LLVM in a threaded context.

DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...

Helper class to build MachineInstr.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Holds all the information related to register banks.

This class implements the register bank concept.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

@ C

The default llvm calling convention, compatible with C.

This is an optimization pass for GlobalISel generic memory operations.

std::function< void(MachineIRBuilder &)> BuildFnTy

Definition CombinerHelper.h:93

SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > OperandBuildSteps

Definition CombinerHelper.h:95

LLVM_ABI bool isOneOrOneSplat(SDValue V, bool AllowUndefs=false)

Return true if the value is a constant 1 integer or a splatted vector of a constant 1 integer (with n...

LLVM_ABI bool isZeroOrZeroSplat(SDValue N, bool AllowUndefs=false)

Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...

Definition CombinerHelper.h:56

bool RematOffset

Definition CombinerHelper.h:60

Definition CombinerHelper.h:58

Definition CombinerHelper.h:59

bool IsPre

Definition CombinerHelper.h:62

Definition CombinerHelper.h:57

InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)

Definition CombinerHelper.h:101

InstructionBuildSteps()=default

Operands to be added to the instruction.

unsigned Opcode

Definition CombinerHelper.h:98

OperandBuildSteps OperandFns

The opcode for the produced instruction.

Definition CombinerHelper.h:99

Definition CombinerHelper.h:105

InstructionStepsMatchInfo(std::initializer_list< InstructionBuildSteps > InstrsToBuild)

Definition CombinerHelper.h:109

InstructionStepsMatchInfo()=default

SmallVector< InstructionBuildSteps, 2 > InstrsToBuild

Describes instructions to be built during a combine.

Definition CombinerHelper.h:107

The LegalityQuery object bundles together all the information that's needed to decide whether a given...

Definition CombinerHelper.h:84

LLT ShiftAmtTy

Definition CombinerHelper.h:89

APInt MaskVal

Definition CombinerHelper.h:86

APInt ShiftAmt

Definition CombinerHelper.h:88

Definition CombinerHelper.h:87

LLT InnerShiftTy

Definition CombinerHelper.h:90

bool Mask

Definition CombinerHelper.h:85

Definition CombinerHelper.h:50

LLT Ty

Definition CombinerHelper.h:51

MachineInstr * MI

Definition CombinerHelper.h:53

unsigned ExtendOpcode

Definition CombinerHelper.h:52

Definition CombinerHelper.h:65

Definition CombinerHelper.h:67

int64_t Imm

Definition CombinerHelper.h:66

unsigned Flags

Definition CombinerHelper.h:69

const RegisterBank * Bank

Definition CombinerHelper.h:68

Definition CombinerHelper.h:72

Definition CombinerHelper.h:73

int64_t Imm

Definition CombinerHelper.h:74

Definition CombinerHelper.h:77

uint64_t ValSum

Definition CombinerHelper.h:81

Definition CombinerHelper.h:80

MachineInstr * Shift2

Definition CombinerHelper.h:79

MachineInstr * Logic

Definition CombinerHelper.h:78