LLVM: include/llvm/MCA/Stages/ExecuteStage.h Source File (original) (raw)

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17#ifndef LLVM_MCA_STAGES_EXECUTESTAGE_H

18#define LLVM_MCA_STAGES_EXECUTESTAGE_H

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25namespace llvm {

26namespace mca {

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28class ExecuteStage final : public Stage {

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31 unsigned NumDispatchedOpcodes;

32 unsigned NumIssuedOpcodes;

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35 bool EnablePressureEvents;

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41 Error issueReadyInstructions();

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46 ExecuteStage(const ExecuteStage &Other) = delete;

47 ExecuteStage &operator=(const ExecuteStage &Other) = delete;

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49public:

52 : HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0),

53 EnablePressureEvents(ShouldPerformBottleneckAnalysis) {}

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84};

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86}

87}

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89#endif

Legalize the Machine IR a function s Machine IR

A scheduler for Processor Resource Units and Processor Resource Groups.

This file defines abstractions used by the Pipeline to model register reads, register writes and inst...

This file defines a stage.

Lightweight error class with error context and mandatory checking.

MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...

void notifyResourceAvailable(const ResourceRef &RR) const

Error cycleStart() override

Called once at the start of each cycle.

bool isAvailable(const InstRef &IR) const override

Returns true if it can execute IR during this cycle.

bool hasWorkToComplete() const override

Returns true if some instructions are still executing this stage.

Definition ExecuteStage.h:61

Error cycleEnd() override

Called once at the end of each cycle.

void notifyInstructionExecuted(const InstRef &IR) const

void notifyInstructionIssued(const InstRef &IR, MutableArrayRef< ResourceUse > Used) const

ExecuteStage(Scheduler &S)

Definition ExecuteStage.h:50

void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const

ExecuteStage(Scheduler &S, bool ShouldPerformBottleneckAnalysis)

Definition ExecuteStage.h:51

void notifyInstructionReady(const InstRef &IR) const

Error execute(InstRef &IR) override

The primary action that this stage performs on instruction IR.

void notifyInstructionPending(const InstRef &IR) const

An InstRef contains both a SourceMgr index and Instruction pair.

Class Scheduler is responsible for issuing instructions to pipeline resources.

std::pair< uint64_t, uint64_t > ResourceRef

This is an optimization pass for GlobalISel generic memory operations.