ExpandPostRAPseudos.cpp Source File (original) (raw)

24using namespace llvm;

26#define DEBUG_TYPE "postrapseudos"

28namespace {

30private:

34public:

35 static char ID;

43 }

48private:

50};

51}

53char ExpandPostRA::ID = 0;

57 "Post-RA pseudo instruction expansion pass", false, false)

61 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&

62 MI->getOperand(1).isImm() &&

63 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&

64 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");

66 Register DstReg = MI->getOperand(0).getReg();

67 Register InsReg = MI->getOperand(2).getReg();

68 assert(->getOperand(2).getSubReg() && "SubIdx on physreg?");

69 unsigned SubIdx = MI->getOperand(3).getImm();

71 assert(SubIdx != 0 && "Invalid index for insert_subreg");

72 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);

75 "Insert destination must be in a physical register");

77 "Inserted value must be in a physical register");

81 if (MI->allDefsAreDead()) {

82 MI->setDesc(TII->get(TargetOpcode::KILL));

83 MI->removeOperand(3);

84 MI->removeOperand(1);

86 return true;

87 }

89 if (DstSubReg == InsReg) {

94 if (DstReg != InsReg) {

95 MI->setDesc(TII->get(TargetOpcode::KILL));

96 MI->removeOperand(3);

97 MI->removeOperand(1);

99 return true;

100 }

102 } else {

104 MI->getOperand(2).isKill());

105

106

108 --CopyMI;

109 CopyMI->addRegisterDefined(DstReg);

111 }

112

115 return true;

116}

117

118

119

120

121bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {

123 << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"

124 << "********** Function: " << MF.getName() << '\n');

127

128 bool MadeChange = false;

129

132

133 if (.isPseudo())

134 continue;

135

136

138 MadeChange = true;

139 continue;

140 }

141

142

143 switch (MI.getOpcode()) {

144 case TargetOpcode::SUBREG_TO_REG:

145 MadeChange |= LowerSubregToReg(&MI);

146 break;

147 case TargetOpcode::COPY:

149 MadeChange = true;

150 break;

151 case TargetOpcode::DBG_VALUE:

152 continue;

153 case TargetOpcode::INSERT_SUBREG:

154 case TargetOpcode::EXTRACT_SUBREG:

155 llvm_unreachable("Sub-register pseudos should have been eliminated.");

156 }

157 }

158 }

159

160 return MadeChange;

161}

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

Represent the analysis usage information of a pass.

AnalysisUsage & addPreservedID(const void *ID)

void setPreservesCFG()

This function should be called by the pass, iff they do not:

bool expandPostRAPseudo(MachineInstr &MI) const override

This function is called for all pseudo instructions that remain after register allocation.

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Emit instructions to copy a pair of physical registers.

instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

virtual const TargetInstrInfo * getInstrInfo() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

char & MachineDominatorsID

MachineDominators - This pass is a machine dominators analysis pass.

char & ExpandPostRAPseudosID

ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

char & MachineLoopInfoID

MachineLoopInfo - This pass is a loop analysis pass.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.