LLVM: lib/CodeGen/ExpandPostRAPseudos.cpp Source File (original) (raw)
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27using namespace llvm;
28
29#define DEBUG_TYPE "postrapseudos"
30
31namespace {
32struct ExpandPostRA {
34
35private:
38
40};
41
43 static char ID;
46 }
47
48 void getAnalysisUsage(AnalysisUsage &AU) const override {
53 }
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55
57};
58}
59
63 if (!ExpandPostRA().run(MF))
65
68 .preserve()
70}
71
72char ExpandPostRALegacy::ID = 0;
74
76 "Post-RA pseudo instruction expansion pass", false, false)
77
80 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
81 MI->getOperand(1).isImm() &&
82 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
83 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
84
85 Register DstReg = MI->getOperand(0).getReg();
86 Register InsReg = MI->getOperand(2).getReg();
87 assert(->getOperand(2).getSubReg() && "SubIdx on physreg?");
88 unsigned SubIdx = MI->getOperand(3).getImm();
89
90 assert(SubIdx != 0 && "Invalid index for insert_subreg");
91 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
92
94 "Insert destination must be in a physical register");
96 "Inserted value must be in a physical register");
97
99
100 if (MI->allDefsAreDead()) {
101 MI->setDesc(TII->get(TargetOpcode::KILL));
102 MI->removeOperand(3);
103 MI->removeOperand(1);
105 return true;
106 }
107
108 if (DstSubReg == InsReg) {
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110
111
112
113 if (DstReg != InsReg) {
114 MI->setDesc(TII->get(TargetOpcode::KILL));
115 MI->removeOperand(3);
116 MI->removeOperand(1);
118 return true;
119 }
121 } else {
122 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
123 MI->getOperand(2).isKill());
124
125
127 --CopyMI;
128 CopyMI->addRegisterDefined(DstReg);
130 }
131
134 return true;
135}
136
137bool ExpandPostRALegacy::runOnMachineFunction(MachineFunction &MF) {
138 return ExpandPostRA().run(MF);
139}
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141
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143
146 << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
147 << "********** Function: " << MF.getName() << '\n');
150
151 bool MadeChange = false;
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155
156 if (.isPseudo())
157 continue;
158
159
161 MadeChange = true;
162 continue;
163 }
164
165
166 switch (MI.getOpcode()) {
167 case TargetOpcode::SUBREG_TO_REG:
168 MadeChange |= LowerSubregToReg(&MI);
169 break;
170 case TargetOpcode::COPY:
172 MadeChange = true;
173 break;
174 case TargetOpcode::DBG_VALUE:
175 continue;
176 case TargetOpcode::INSERT_SUBREG:
177 case TargetOpcode::EXTRACT_SUBREG:
178 llvm_unreachable("Sub-register pseudos should have been eliminated.");
179 }
180 }
181 }
182
183 return MadeChange;
184}
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const TargetInstrInfo & TII
Register const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Represents analyses that only rely on functions' control flow.
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Definition ExpandPostRAPseudos.cpp:61
MachineInstrBundleIterator< MachineInstr > iterator
Analysis pass which computes a MachineDominatorTree.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Representation of each machine instruction.
static LLVM_ABI PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
A set of analyses that are preserved following a run of a transformation pass.
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
PreservedAnalyses & preserveSet()
Mark an analysis set as preserved.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
TargetInstrInfo - Interface to description of machine instruction set.
void lowerCopy(MachineInstr *MI, const TargetRegisterInfo *TRI) const
This function defines the logic to lower COPY instruction to target specific instruction(s).
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LLVM_ABI char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
Definition ExpandPostRAPseudos.cpp:73
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
LLVM_ABI char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LLVM_ABI void initializeExpandPostRALegacyPass(PassRegistry &)