LLVM: lib/Target/AMDGPU/GCNHazardRecognizer.h Source File (original) (raw)
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13#ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
14#define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
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20#include
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22namespace llvm {
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33public:
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38private:
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40 bool IsHazardRecognizerMode;
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46 std::list<MachineInstr*> EmittedInstrs;
52 bool RunLdsBranchVmemWARHazardFixup;
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60 void resetClause() {
61 ClauseUses.reset();
62 ClauseDefs.reset();
63 }
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69 unsigned getMFMAPipelineWaitStates(const MachineInstr &MI) const;
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73 void processBundle();
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82 int getWaitStatesSinceDef(unsigned Reg, IsHazardFn IsHazardDef, int Limit);
83 int getWaitStatesSinceSetReg(IsHazardFn IsHazard, int Limit);
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85 int checkSoftClauseHazards(MachineInstr *SMEM);
89 int checkDivFMasHazards(MachineInstr *DivFMas);
90 int checkGetRegHazards(MachineInstr *GetRegInstr);
91 int checkSetRegHazards(MachineInstr *SetRegInstr);
98 int checkReadM0Hazards(MachineInstr *SMovRel);
100 int checkFPAtomicToDenormModeHazard(MachineInstr *MI);
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103 bool emitVNops(MachineInstr *MI, int WaitStatesNeeded);
112 bool fixVALUPartialForwardingHazard(MachineInstr *MI);
114 bool fixVALUTransCoexecutionHazards(MachineInstr *MI);
121 bool fixDsAtomicAsyncBarrierArriveB64(MachineInstr *MI);
122 bool fixScratchBaseForwardingHazard(MachineInstr *MI);
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148public:
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161 void Reset() override;
162};
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164}
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166#endif
unsigned const MachineRegisterInfo * MRI
This file implements the BitVector class.
static int getWaitStatesSince(GCNHazardRecognizer::IsHazardFn IsHazard, const MachineBasicBlock *MBB, MachineBasicBlock::const_reverse_instr_iterator I, int WaitStates, GCNHazardRecognizer::IsExpiredFn IsExpired, DenseSet< const MachineBasicBlock * > &Visited, GCNHazardRecognizer::GetNumWaitStatesFn GetNumWaitStates=SIInstrInfo::getNumWaitStates)
void EmitNoop() override
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
unsigned PreEmitNoops(MachineInstr *) override
This overload will be used when the hazard recognizer is being used by a non-scheduling pass,...
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
function_ref< bool(const MachineInstr &)> IsHazardFn
Definition GCNHazardRecognizer.h:34
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
function_ref< unsigned int(const MachineInstr &)> GetNumWaitStatesFn
Definition GCNHazardRecognizer.h:36
unsigned PreEmitNoopsCommon(MachineInstr *)
function_ref< bool(const MachineInstr &, int WaitStates)> IsExpiredFn
Definition GCNHazardRecognizer.h:35
bool ShouldPreferAnother(SUnit *SU) override
ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
GCNHazardRecognizer(const MachineFunction &MF)
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
bool atIssueLimit() const override
atIssueLimit - Return true if no more instructions may be issued in this cycle.
Definition GCNHazardRecognizer.h:151
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Scheduling unit. This is a node in the scheduling DAG.
ScheduleHazardRecognizer()=default
Provide an instruction scheduling machine model to CodeGen passes.
An efficient, type-erasing, non-owning reference to a callable.
This is an optimization pass for GlobalISel generic memory operations.