LLVM: lib/Target/AMDGPU/GCNPreRAOptimizations.cpp File Reference (original) (raw)
This pass combines split register tuple initialization into a single pseudo: More...
This pass combines split register tuple initialization into a single pseudo:
undef %0.sub1:sreg_64 = S_MOV_B32 1 %0.sub0:sreg_64 = S_MOV_B32 2 => %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 0x200000001
This is to allow rematerialization of a value instead of spilling. It is supposed to be done after register coalescer to allow it to do its job and before actual register allocation to allow rematerialization.
Right now the pass only handles 64 bit SGPRs with immediate initializers, although the same shall be possible with other register classes and instructions if necessary.
This pass also adds register allocation hints to COPY. The hints will be post-processed by SIRegisterInfo::getRegAllocationHints. When using True16, we often see COPY moving a 16-bit value between a VGPR_32 and a VGPR_16. If we use the VGPR_16 that corresponds to the lo16 bits of the VGPR_32, the COPY can be completely eliminated.
Definition in file GCNPreRAOptimizations.cpp.