LLVM: lib/Target/AMDGPU/GCNSchedStrategy.h Source File (original) (raw)
1
2
3
4
5
6
7
8
9
10
11
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
14#define LLVM_LIB_TARGET_AMDGPU_GCNSCHEDSTRATEGY_H
15
21
22namespace llvm {
23
28
37
38#ifndef NDEBUG
40#endif
41
42
43
44
46protected:
48
52 bool IsBottomUp);
53
57 unsigned VGPRPressure, bool IsBottomUp);
58
59
60
61
62
63
64
65
66
69
72
74
76
78
80
82
84
85
87
88
90
91
93
94
96
97public:
98
99
101
102
103
105
106
107
108
110
111
113
114
116
118
120
122
124
126
128
130
132
134
136
138
139
141
143
145
147
149};
150
151
152
154public:
156 bool IsLegacyScheduler = false);
157};
158
159
160
162protected:
165
166public:
168};
169
170
171
173protected:
176
177public:
179};
180
182 unsigned ScheduleLength;
183 unsigned BubbleCycles;
184
185public:
188 : ScheduleLength(L), BubbleCycles(BC) {}
189 unsigned getLength() const { return ScheduleLength; }
190 unsigned getBubbles() const { return BubbleCycles; }
192 unsigned Metric = (BubbleCycles * ScaleFactor) / ScheduleLength;
193
194
195 return Metric ? Metric : 1;
196 }
198};
199
201 dbgs() << "\n Schedule Metric (scaled by "
205 return OS;
206}
207
208class GCNScheduleDAGMILive;
211
212
214
216
217 bool IsLiveOut;
218
219public:
222 : DAG(GCNDAG), IsLiveOut(LiveOut) {}
223
225
226
228 assert(IdxToInstruction.contains(RegionIdx));
230 return RegionLiveRegMap[Key];
231 }
232};
233
234
235
237 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>;
238
247
249
251
252
253 unsigned StartingOccupancy;
254
255
256 unsigned MinOccupancy;
257
258
260
261
263
264
265
267
268
270
271
273
274
276
277
279
280
282
283
284
286
287
288
290 getRegionLiveOutMap() const;
291
292
293
294
296
297
298 GCNRegPressure getRealRegPressure(unsigned RegionIdx) const;
299
300
302
303
304
305
306
310
311 void runSchedStages();
312
313 std::unique_ptr createSchedStage(GCNSchedStageID SchedStageID);
314
315public:
317 std::unique_ptr S);
318
320
322};
323
324
326protected:
328
330
332
334
336
338
339
341
342
344
345
347
348
350
351
353
354 std::vector<std::unique_ptr> SavedMutations;
355
357
358public:
359
360
362
363
365
366
367
369
370
372
373
375
376
378
379
385
386
388
389
393
394
396
397
399
400
402
404
406};
407
415
417private:
418
419 unsigned InitialOccupancy;
420
421 unsigned TempTargetOccupancy;
422
423 bool IsAnyRegionScheduled;
424
425public:
427
429
431
433
436};
437
438
439
440
442public:
444
446
448
451};
452
453
454
455
456
457
458
460private:
461
462 struct RematInstruction {
463
464
466
467
469
470
472
474 };
475
476
477
479
481
483
484
486
487
489
490
492
493
494 std::optional TargetOcc;
495
496
497 unsigned AchievedOcc;
498
499
500
501
502
503 bool canIncreaseOccupancyOrReduceSpill();
504
505
507
508
509
510
511 void rematerialize();
512
513
514
515
517
518public:
520
522
524
527};
528
536
545
547private:
548 std::vector<std::unique_ptr> SavedMutations;
549
550 bool HasIGLPInstrs = false;
551
552public:
554
556
558 std::unique_ptr S,
560};
561
562}
563
564#endif
MachineInstrBuilder & UseMI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the DenseMap class.
This file defines the GCNRegPressure class, which tracks registry pressure by bookkeeping number of S...
This file implements a map that provides insertion order iteration.
bool initGCNSchedStage() override
bool shouldRevertScheduling(unsigned WavesAfter) override
bool initGCNRegion() override
ClusteredLowOccStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition GCNSchedStrategy.h:449
GCNMaxILPSchedStrategy(const MachineSchedContext *C)
bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const override
Apply a set of heuristics to a new candidate.
bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const override
GCNMaxMemoryClauseSchedStrategy tries best to clause memory instructions as much as possible.
GCNMaxMemoryClauseSchedStrategy(const MachineSchedContext *C)
GCNMaxOccupancySchedStrategy(const MachineSchedContext *C, bool IsLegacyScheduler=false)
void finalizeSchedule() override
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
void schedule() override
Orders nodes according to selected style.
GCNPostScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags)
DenseMap< unsigned, LaneBitmask > LiveRegSet
Definition GCNSchedStrategy.h:325
virtual bool initGCNRegion()
GCNSchedStrategy & S
Definition GCNSchedStrategy.h:329
GCNRegPressure PressureBefore
Definition GCNSchedStrategy.h:349
bool isRegionWithExcessRP() const
Definition GCNSchedStrategy.h:390
unsigned getRegionIdx()
Definition GCNSchedStrategy.h:395
bool mayCauseSpilling(unsigned WavesAfter)
ScheduleMetrics getScheduleMetrics(const std::vector< SUnit > &InputSchedule)
GCNScheduleDAGMILive & DAG
Definition GCNSchedStrategy.h:327
const GCNSchedStageID StageID
Definition GCNSchedStrategy.h:337
std::vector< MachineInstr * > Unsched
Definition GCNSchedStrategy.h:346
GCNRegPressure PressureAfter
Definition GCNSchedStrategy.h:352
MachineFunction & MF
Definition GCNSchedStrategy.h:331
SIMachineFunctionInfo & MFI
Definition GCNSchedStrategy.h:333
unsigned RegionIdx
Definition GCNSchedStrategy.h:343
void advanceRegion()
Definition GCNSchedStrategy.h:403
unsigned computeSUnitReadyCycle(const SUnit &SU, unsigned CurrCycle, DenseMap< unsigned, unsigned > &ReadyCycles, const TargetSchedModel &SM)
virtual ~GCNSchedStage()=default
virtual void finalizeGCNSchedStage()
virtual bool initGCNSchedStage()
virtual bool shouldRevertScheduling(unsigned WavesAfter)
std::vector< std::unique_ptr< ScheduleDAGMutation > > SavedMutations
Definition GCNSchedStrategy.h:354
GCNSchedStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
MachineBasicBlock * CurrentMBB
Definition GCNSchedStrategy.h:340
const GCNSubtarget & ST
Definition GCNSchedStrategy.h:335
This is a minimal scheduler strategy.
Definition GCNSchedStrategy.h:45
const unsigned HighRPSGPRBias
Definition GCNSchedStrategy.h:112
GCNDownwardRPTracker DownwardTracker
Definition GCNSchedStrategy.h:92
GCNSchedStrategy(const MachineSchedContext *C)
SmallVector< GCNSchedStageID, 4 > SchedStages
Definition GCNSchedStrategy.h:86
bool HasHighPressure
Definition GCNSchedStrategy.h:100
unsigned SGPRCriticalLimit
Definition GCNSchedStrategy.h:117
std::vector< unsigned > MaxPressure
Definition GCNSchedStrategy.h:75
bool hasNextStage() const
unsigned TargetOccupancy
Definition GCNSchedStrategy.h:81
SUnit * pickNodeBidirectional(bool &IsTopNode, bool &PickedPending)
bool KnownExcessRP
Definition GCNSchedStrategy.h:104
GCNSchedStageID getCurrentStage()
unsigned VGPRExcessLimit
Definition GCNSchedStrategy.h:79
MachineFunction * MF
Definition GCNSchedStrategy.h:83
bool tryPendingCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const
Evaluates instructions in the pending queue using a subset of scheduling heuristics.
SmallVectorImpl< GCNSchedStageID >::iterator CurrentStage
Definition GCNSchedStrategy.h:89
unsigned VGPRCriticalLimit
Definition GCNSchedStrategy.h:119
void schedNode(SUnit *SU, bool IsTopNode) override
Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an instruction and updated scheduled/rem...
GCNDownwardRPTracker * getDownwardTracker()
Definition GCNSchedStrategy.h:146
unsigned SGPRLimitBias
Definition GCNSchedStrategy.h:121
unsigned SGPRExcessLimit
Definition GCNSchedStrategy.h:77
std::vector< unsigned > Pressure
Definition GCNSchedStrategy.h:73
void initialize(ScheduleDAGMI *DAG) override
Initialize the strategy after building the DAG for a new region.
GCNUpwardRPTracker UpwardTracker
Definition GCNSchedStrategy.h:95
void printCandidateDecision(const SchedCandidate &Current, const SchedCandidate &Preferred)
const unsigned HighRPVGPRBias
Definition GCNSchedStrategy.h:115
void pickNodeFromQueue(SchedBoundary &Zone, const CandPolicy &ZonePolicy, const RegPressureTracker &RPTracker, SchedCandidate &Cand, bool &IsPending, bool IsBottomUp)
unsigned ErrorMargin
Definition GCNSchedStrategy.h:109
void initCandidate(SchedCandidate &Cand, SUnit *SU, bool AtTop, const RegPressureTracker &RPTracker, const SIRegisterInfo *SRI, unsigned SGPRPressure, unsigned VGPRPressure, bool IsBottomUp)
unsigned getTargetOccupancy()
Definition GCNSchedStrategy.h:133
void setTargetOccupancy(unsigned Occ)
Definition GCNSchedStrategy.h:135
unsigned VGPRLimitBias
Definition GCNSchedStrategy.h:123
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule, or return NULL.
GCNUpwardRPTracker * getUpwardTracker()
Definition GCNSchedStrategy.h:148
GCNSchedStageID getNextStage() const
Definition GCNSchedStrategy.h:239
void finalizeSchedule() override
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
friend class RegionPressureMap
Definition GCNSchedStrategy.h:246
friend class GCNSchedStage
Definition GCNSchedStrategy.h:240
void schedule() override
Orders nodes according to selected style.
GCNScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
friend class PreRARematStage
Definition GCNSchedStrategy.h:244
friend class ClusteredLowOccStage
Definition GCNSchedStrategy.h:243
friend class ILPInitialScheduleStage
Definition GCNSchedStrategy.h:245
friend class OccInitialScheduleStage
Definition GCNSchedStrategy.h:241
friend class UnclusteredHighRPStage
Definition GCNSchedStrategy.h:242
GenericScheduler(const MachineSchedContext *C)
bool shouldRevertScheduling(unsigned WavesAfter) override
ILPInitialScheduleStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition GCNSchedStrategy.h:533
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
This class implements a map that also provides access to all stored values in a deterministic order.
bool shouldRevertScheduling(unsigned WavesAfter) override
MemoryClauseInitialScheduleStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition GCNSchedStrategy.h:541
bool shouldRevertScheduling(unsigned WavesAfter) override
OccInitialScheduleStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition GCNSchedStrategy.h:412
PreRARematStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition GCNSchedStrategy.h:525
bool shouldRevertScheduling(unsigned WavesAfter) override
bool initGCNRegion() override
bool initGCNSchedStage() override
Track the current register pressure at some position in the instruction stream, and remember the high...
GCNRPTracker::LiveRegSet & getLiveRegsForRegionIdx(unsigned RegionIdx)
Definition GCNSchedStrategy.h:227
RegionPressureMap()=default
RegionPressureMap(GCNScheduleDAGMILive *GCNDAG, bool LiveOut)
Definition GCNSchedStrategy.h:221
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Scheduling unit. This is a node in the scheduling DAG.
Each Scheduling boundary is associated with ready queues.
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
ScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags)
Definition GCNSchedStrategy.h:181
ScheduleMetrics()=default
unsigned getBubbles() const
Definition GCNSchedStrategy.h:190
ScheduleMetrics(unsigned L, unsigned BC)
Definition GCNSchedStrategy.h:187
unsigned getLength() const
Definition GCNSchedStrategy.h:189
static const unsigned ScaleFactor
Definition GCNSchedStrategy.h:197
unsigned getMetric() const
Definition GCNSchedStrategy.h:191
Implements a dense probed hash-table based set with some number of buckets stored inline.
typename SuperClass::iterator iterator
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Provide an instruction scheduling machine model to CodeGen passes.
UnclusteredHighRPStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
Definition GCNSchedStrategy.h:434
bool initGCNSchedStage() override
bool initGCNRegion() override
void finalizeGCNSchedStage() override
bool shouldRevertScheduling(unsigned WavesAfter) override
This class implements an extremely fast bulk output stream that can only output to a stream.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > RegionBoundaries
A region's boundaries i.e.
Definition GCNSchedStrategy.h:236
GCNSchedStageID
Definition GCNSchedStrategy.h:29
@ UnclusteredHighRPReschedule
Definition GCNSchedStrategy.h:31
@ MemoryClauseInitialSchedule
Definition GCNSchedStrategy.h:35
@ ILPInitialSchedule
Definition GCNSchedStrategy.h:34
@ PreRARematerialize
Definition GCNSchedStrategy.h:33
@ OccInitialSchedule
Definition GCNSchedStrategy.h:30
@ ClusteredLowOccupancyReschedule
Definition GCNSchedStrategy.h:32
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Policy for scheduling the next instruction in the candidate's zone.
Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of p...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...