HexagonAsmPrinter.cpp Source File (original) (raw)

49#include

50#include

51#include

53using namespace llvm;

55namespace llvm {

60}

62#define DEBUG_TYPE "asm-printer"

68 unsigned Pair = *RI->superregs(Reg).begin();

70 return Pair;

71}

78 default:

82 return;

85 return;

88 return;

91 return;

94 return;

95 }

96}

100

101

102

103

107 return false;

109}

110

111

113 const char *ExtraCode,

115

116 if (ExtraCode && ExtraCode[0]) {

117 if (ExtraCode[1] != 0)

118 return true;

119

120 switch (ExtraCode[0]) {

121 default:

122

124 case 'L':

125 case 'H': {

130 return true;

132

133 if (Hexagon::DoubleRegsRegClass.contains(RegNumber))

134 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?

135 Hexagon::isub_lo :

136 Hexagon::isub_hi);

138 return false;

139 }

140 case 'I':

141

142

143 if (MI->getOperand(OpNo).isImm())

144 OS << "i";

145 return false;

146 }

147 }

148

150 return false;

151}

152

154 unsigned OpNo,

155 const char *ExtraCode,

157 if (ExtraCode && ExtraCode[0])

158 return true;

159

162

163 if (Base.isReg())

165 else

167

168 if (Offset.isImm()) {

170 O << "+#" << Offset.getImm();

171 } else {

173 }

174

175 return false;

176}

177

183 if (Imm.getExpr()->evaluateAsAbsolute(Value)) {

185 std::string ImmString;

187 if (AlignSize == 8) {

188 Name = ".CONST_0000000000000000";

189 sectionPrefix = ".gnu.linkonce.l8";

190 ImmString = utohexstr(Value);

191 } else {

192 Name = ".CONST_00000000";

193 sectionPrefix = ".gnu.linkonce.l4";

194 ImmString = utohexstr(static_cast<uint32_t>(Value));

195 }

196

197 std::string symbolName =

198 Name.drop_back(ImmString.size()).str() + ImmString;

199 std::string sectionName = sectionPrefix.str() + symbolName;

200

204

206 if (Sym->isUndefined()) {

211 }

212 } else {

213 assert(Imm.isExpr() && "Expected expression and found none");

216 MCSymbol *MOSymbol = nullptr;

219 else if (MO.isCPI())

221 else if (MO.isJTI())

223 else

225

227 std::string LitaName = ".CONST_" + SymbolName.str();

228

231

234 if (Sym->isUndefined()) {

237 OutStreamer.emitValue(Imm.getExpr(), AlignSize);

239 }

240 }

241 return Sym;

242}

243

245 unsigned VectorSize, MCContext &Ctx) {

248 for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {

249 if (i != OpNo) {

251 continue;

252 }

255 int32_t V = cast(HE->getExpr())->getValue();

259 }

260 return T;

261}

262

265 MCInst &MappedInst = static_cast <MCInst &>(Inst);

269 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;

270

272 default:

273 return;

274

275 case Hexagon::A2_iconst: {

276 Inst.setOpcode(Hexagon::A2_addi);

285 break;

286 }

287

288 case Hexagon::A2_tfrf: {

290 Inst.setOpcode(Hexagon::A2_paddif);

292 break;

293 }

294

295 case Hexagon::A2_tfrt: {

297 Inst.setOpcode(Hexagon::A2_paddit);

299 break;

300 }

301

302 case Hexagon::A2_tfrfnew: {

304 Inst.setOpcode(Hexagon::A2_paddifnew);

306 break;

307 }

308

309 case Hexagon::A2_tfrtnew: {

311 Inst.setOpcode(Hexagon::A2_padditnew);

313 break;

314 }

315

316 case Hexagon::A2_zxtb: {

318 Inst.setOpcode(Hexagon::A2_andir);

320 break;

321 }

322

323

324 case Hexagon::CONST64:

328

331

332 OutStreamer->switchSection(Current.first, Current.second);

335 TmpInst.setOpcode(Hexagon::L2_loadrdgp);

339 MappedInst = TmpInst;

340

341 }

342 break;

343 case Hexagon::CONST32:

349 OutStreamer->switchSection(Current.first, Current.second);

352 TmpInst.setOpcode(Hexagon::L2_loadrigp);

356 MappedInst = TmpInst;

357 }

358 break;

359

360

361

362

363 case Hexagon::C2_pxfer_map: {

365 MappedInst.setOpcode(Hexagon::C2_or);

367 return;

368 }

369

370

371

372

373 case Hexagon::M2_vrcmpys_acc_s1: {

375 assert(Rt.isReg() && "Expected register and none was found");

377 if (Reg & 1)

378 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);

379 else

380 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);

382 return;

383 }

384 case Hexagon::M2_vrcmpys_s1: {

386 assert(Rt.isReg() && "Expected register and none was found");

388 if (Reg & 1)

389 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);

390 else

391 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);

393 return;

394 }

395

396 case Hexagon::M2_vrcmpys_s1rp: {

398 assert(Rt.isReg() && "Expected register and none was found");

400 if (Reg & 1)

401 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);

402 else

403 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);

405 return;

406 }

407

408 case Hexagon::A4_boundscheck: {

410 assert(Rs.isReg() && "Expected register and none was found");

412 if (Reg & 1)

413 MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);

414 else

415 MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);

417 return;

418 }

419

420 case Hexagon::PS_call_nr:

421 Inst.setOpcode(Hexagon::J2_call);

422 break;

423

424 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {

426 int64_t Imm;

428 bool Success = Expr->evaluateAsAbsolute(Imm);

429 assert(Success && "Expected immediate and none was found");

432 if (Imm == 0) {

433 TmpInst.setOpcode(Hexagon::S2_vsathub);

436 MappedInst = TmpInst;

437 return;

438 }

439 TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);

446 MappedInst = TmpInst;

447 return;

448 }

449

450 case Hexagon::S5_vasrhrnd_goodsyntax:

451 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {

454 int64_t Imm;

455 bool Success = Expr->evaluateAsAbsolute(Imm);

456 assert(Success && "Expected immediate and none was found");

459 if (Imm == 0) {

460 TmpInst.setOpcode(Hexagon::A2_combinew);

465

468 MappedInst = TmpInst;

469 return;

470 }

471

472 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)

473 TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);

474 else

475 TmpInst.setOpcode(Hexagon::S5_vasrhrnd);

482 MappedInst = TmpInst;

483 return;

484 }

485

486

487 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {

490 int64_t Imm;

491 bool Success = Expr->evaluateAsAbsolute(Imm);

492 assert(Success && "Expected immediate and none was found");

495 if (Imm == 0) {

496 TmpInst.setOpcode(Hexagon::A2_tfr);

499 MappedInst = TmpInst;

500 return;

501 }

502 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);

509 MappedInst = TmpInst;

510 return;

511 }

512

513

514 case Hexagon::A2_tfrpi: {

518

519 TmpInst.setOpcode(Hexagon::A2_combineii);

521 int64_t Imm;

522 bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);

523 if (Success && Imm < 0) {

527 } else {

531 }

533 MappedInst = TmpInst;

534 return;

535 }

536

537

538 case Hexagon::A2_tfrp: {

543

545 MappedInst.setOpcode(Hexagon::A2_combinew);

546 return;

547 }

548

549 case Hexagon::A2_tfrpt:

550 case Hexagon::A2_tfrpf: {

555

558 ? Hexagon::C2_ccombinewt

559 : Hexagon::C2_ccombinewf);

560 return;

561 }

562

563 case Hexagon::A2_tfrptnew:

564 case Hexagon::A2_tfrpfnew: {

569

572 ? Hexagon::C2_ccombinewnewt

573 : Hexagon::C2_ccombinewnewf);

574 return;

575 }

576

577 case Hexagon::M2_mpysmi: {

579 MCExpr const *Expr = Imm.getExpr();

581 bool Success = Expr->evaluateAsAbsolute(Value);

584 if (Value < 0 && Value > -256) {

585 MappedInst.setOpcode(Hexagon::M2_mpysin);

588 } else

589 MappedInst.setOpcode(Hexagon::M2_mpysip);

590 return;

591 }

592

593 case Hexagon::A2_addsp: {

595 assert(Rt.isReg() && "Expected register and none was found");

597 if (Reg & 1)

598 MappedInst.setOpcode(Hexagon::A2_addsph);

599 else

600 MappedInst.setOpcode(Hexagon::A2_addspl);

602 return;

603 }

604

605 case Hexagon::V6_vd0: {

608 "Expected register and none was found");

609

610 TmpInst.setOpcode(Hexagon::V6_vxor);

614 MappedInst = TmpInst;

615 return;

616 }

617

618 case Hexagon::V6_vdd0: {

621 "Expected register and none was found");

622

623 TmpInst.setOpcode(Hexagon::V6_vsubw_dv);

627 MappedInst = TmpInst;

628 return;

629 }

630

631 case Hexagon::V6_vL32Ub_pi:

632 case Hexagon::V6_vL32b_cur_pi:

633 case Hexagon::V6_vL32b_nt_cur_pi:

634 case Hexagon::V6_vL32b_pi:

635 case Hexagon::V6_vL32b_nt_pi:

636 case Hexagon::V6_vL32b_nt_tmp_pi:

637 case Hexagon::V6_vL32b_tmp_pi:

639 return;

640

641 case Hexagon::V6_vL32Ub_ai:

642 case Hexagon::V6_vL32b_ai:

643 case Hexagon::V6_vL32b_cur_ai:

644 case Hexagon::V6_vL32b_nt_ai:

645 case Hexagon::V6_vL32b_nt_cur_ai:

646 case Hexagon::V6_vL32b_nt_tmp_ai:

647 case Hexagon::V6_vL32b_tmp_ai:

649 return;

650

651 case Hexagon::V6_vS32Ub_pi:

652 case Hexagon::V6_vS32b_new_pi:

653 case Hexagon::V6_vS32b_nt_new_pi:

654 case Hexagon::V6_vS32b_nt_pi:

655 case Hexagon::V6_vS32b_pi:

657 return;

658

659 case Hexagon::V6_vS32Ub_ai:

660 case Hexagon::V6_vS32b_ai:

661 case Hexagon::V6_vS32b_new_ai:

662 case Hexagon::V6_vS32b_nt_ai:

663 case Hexagon::V6_vS32b_nt_new_ai:

665 return;

666

667 case Hexagon::V6_vL32b_cur_npred_pi:

668 case Hexagon::V6_vL32b_cur_pred_pi:

669 case Hexagon::V6_vL32b_npred_pi:

670 case Hexagon::V6_vL32b_nt_cur_npred_pi:

671 case Hexagon::V6_vL32b_nt_cur_pred_pi:

672 case Hexagon::V6_vL32b_nt_npred_pi:

673 case Hexagon::V6_vL32b_nt_pred_pi:

674 case Hexagon::V6_vL32b_nt_tmp_npred_pi:

675 case Hexagon::V6_vL32b_nt_tmp_pred_pi:

676 case Hexagon::V6_vL32b_pred_pi:

677 case Hexagon::V6_vL32b_tmp_npred_pi:

678 case Hexagon::V6_vL32b_tmp_pred_pi:

680 return;

681

682 case Hexagon::V6_vL32b_cur_npred_ai:

683 case Hexagon::V6_vL32b_cur_pred_ai:

684 case Hexagon::V6_vL32b_npred_ai:

685 case Hexagon::V6_vL32b_nt_cur_npred_ai:

686 case Hexagon::V6_vL32b_nt_cur_pred_ai:

687 case Hexagon::V6_vL32b_nt_npred_ai:

688 case Hexagon::V6_vL32b_nt_pred_ai:

689 case Hexagon::V6_vL32b_nt_tmp_npred_ai:

690 case Hexagon::V6_vL32b_nt_tmp_pred_ai:

691 case Hexagon::V6_vL32b_pred_ai:

692 case Hexagon::V6_vL32b_tmp_npred_ai:

693 case Hexagon::V6_vL32b_tmp_pred_ai:

695 return;

696

697 case Hexagon::V6_vS32Ub_npred_pi:

698 case Hexagon::V6_vS32Ub_pred_pi:

699 case Hexagon::V6_vS32b_new_npred_pi:

700 case Hexagon::V6_vS32b_new_pred_pi:

701 case Hexagon::V6_vS32b_npred_pi:

702 case Hexagon::V6_vS32b_nqpred_pi:

703 case Hexagon::V6_vS32b_nt_new_npred_pi:

704 case Hexagon::V6_vS32b_nt_new_pred_pi:

705 case Hexagon::V6_vS32b_nt_npred_pi:

706 case Hexagon::V6_vS32b_nt_nqpred_pi:

707 case Hexagon::V6_vS32b_nt_pred_pi:

708 case Hexagon::V6_vS32b_nt_qpred_pi:

709 case Hexagon::V6_vS32b_pred_pi:

710 case Hexagon::V6_vS32b_qpred_pi:

712 return;

713

714 case Hexagon::V6_vS32Ub_npred_ai:

715 case Hexagon::V6_vS32Ub_pred_ai:

716 case Hexagon::V6_vS32b_new_npred_ai:

717 case Hexagon::V6_vS32b_new_pred_ai:

718 case Hexagon::V6_vS32b_npred_ai:

719 case Hexagon::V6_vS32b_nqpred_ai:

720 case Hexagon::V6_vS32b_nt_new_npred_ai:

721 case Hexagon::V6_vS32b_nt_new_pred_ai:

722 case Hexagon::V6_vS32b_nt_npred_ai:

723 case Hexagon::V6_vS32b_nt_nqpred_ai:

724 case Hexagon::V6_vS32b_nt_pred_ai:

725 case Hexagon::V6_vS32b_nt_qpred_ai:

726 case Hexagon::V6_vS32b_pred_ai:

727 case Hexagon::V6_vS32b_qpred_ai:

729 return;

730

731

732 case Hexagon::V6_vS32b_srls_ai:

734 return;

735

736 case Hexagon::V6_vS32b_srls_pi:

738 return;

739 }

740}

741

742

744 Hexagon_MC::verifyInstructionPredicates(MI->getOpcode(),

746

751

752 if (MI->isBundle()) {

755

756 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)

757 if (!MII->isDebugInstr() && !MII->isImplicitDef())

759 } else {

761 }

762

765 if (MI->isBundle() && HII.getBundleNoShuf(*MI))

767

770 MCB, nullptr);

771 assert(Ok); (void)Ok;

773 return;

775}

776

779 emitAttributes();

780}

781

787}

788

789void HexagonAsmPrinter::emitAttributes() {

793}

794

796 static const int8_t NoopsInSledCount = 4;

797

798

799

800

801

802

803

804

805

806

807

808

809

810

811

812

813

814

815

816

817

818

821

823 SledJump->setOpcode(Hexagon::J2_jump);

827

828

829 MCInst SledJumpPacket;

830 SledJumpPacket.setOpcode(Hexagon::BUNDLE);

833

835

836

837

839

842}

843

846}

847

850}

851

854}

855

858}

#define LLVM_EXTERNAL_VISIBILITY

static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonAsmPrinter()

static MCSymbol * smallData(AsmPrinter &AP, const MachineInstr &MI, MCStreamer &OutStreamer, const MCOperand &Imm, int AlignSize, const MCSubtargetInfo &STI)

static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo, unsigned VectorSize, MCContext &Ctx)

static unsigned getHexagonRegisterPair(unsigned Reg, const MCRegisterInfo *RI)

unsigned const TargetRegisterInfo * TRI

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

This class is intended to be used as a driving class for all asm writers.

MCSymbol * getSymbol(const GlobalValue *GV) const

void emitNops(unsigned N)

Emit N NOP instructions.

void EmitToStreamer(MCStreamer &S, const MCInst &Inst)

TargetMachine & TM

Target machine description.

virtual MCSymbol * GetCPISymbol(unsigned CPID) const

Return the symbol for the specified constant pool entry.

virtual void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &OS)

Print the MachineOperand as a symbol.

const MCAsmInfo * MAI

Target Asm Printer information.

MachineFunction * MF

The current machine function.

virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const

Return true if the basic block has exactly one predecessor and the control transfer mechanism between...

MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const

Return the symbol for the specified jump table entry.

void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)

MCContext & OutContext

This is the context for the output file that we are streaming.

std::unique_ptr< MCStreamer > OutStreamer

This is the MCStreamer object for the file we are generating.

const MCSubtargetInfo & getSubtargetInfo() const

Return information about subtarget.

virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)

Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.

void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)

void EmitSled(const MachineInstr &MI, SledKind Kind)

void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)

bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override

Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...

bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override

Return true if the basic block has exactly one predecessor and the control transfer mechanism between...

bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override

PrintAsmOperand - Print out an operand for an inline asm expression.

void emitInstruction(const MachineInstr *MI) override

Print out a single Hexagon MI to the current output stream.

void emitEndOfAsmFile(Module &M) override

This virtual method can be overridden by targets that want to emit something at the end of their file...

void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)

void emitStartOfAsmFile(Module &M) override

This virtual method can be overridden by targets that want to emit something at the start of their fi...

void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)

void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB)

static char const * getRegisterName(MCRegister Reg)

static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)

const HexagonInstrInfo * getInstrInfo() const override

void emitTargetAttributes(const MCSubtargetInfo &STI)

virtual void finishAttributeSection()

static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

MCSymbol * createTempSymbol()

Create a temporary symbol with a unique name.

MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)

MCSymbol * getOrCreateSymbol(const Twine &Name)

Lookup the symbol inside with the specified Name.

Base class for the full range of assembler expressions which are needed for parsing.

Instances of this class represent a single low-level machine instruction.

unsigned getNumOperands() const

unsigned getOpcode() const

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

Interface to description of machine instruction set.

Instances of this class represent operands of the MCInst class.

static MCOperand createExpr(const MCExpr *Val)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

void setReg(MCRegister Reg)

Set the register number.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

static MCOperand createInst(const MCInst *Val)

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

iterator_range< MCSuperRegIterator > superregs(MCRegister Reg) const

Return an iterator range over all super-registers of Reg, excluding Reg.

uint16_t getEncodingValue(MCRegister Reg) const

Returns the encoding for Reg.

MCRegister getSubReg(MCRegister Reg, unsigned Idx) const

Returns the physical register number of sub-register "Index" for physical register RegNo.

This represents a section on linux, lots of unix variants and some bare metal systems.

Streaming machine code generation interface.

virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0

Add the given Attribute to Symbol.

MCContext & getContext() const

void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())

virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())

Emit a label for Symbol into the current section.

virtual void emitIntValue(uint64_t Value, unsigned Size)

Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.

virtual void emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit=0)

Emit nops until the byte alignment ByteAlignment is reached.

virtual void switchSection(MCSection *Section, uint32_t Subsec=0)

Set the current section where code is being emitted to Section.

Generic base class for all target subtargets.

static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

void print(raw_ostream &OS, const MCAsmInfo *MAI) const

print - Print the value to the stream OS.

StringRef getName() const

getName - Get the symbol name.

static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())

MCSymbol * getSymbol() const

Return the MCSymbol for this basic block.

bool hasAddressTaken() const

Test whether this block is used as something other than the target of a terminator,...

instr_iterator instr_end()

Instructions::const_iterator const_instr_iterator

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

const GlobalValue * getGlobal() const

bool isReg() const

isReg - Tests if this is a MO_Register operand.

MachineBasicBlock * getMBB() const

bool isCPI() const

isCPI - Tests if this is a MO_ConstantPoolIndex operand.

bool isJTI() const

isJTI - Tests if this is a MO_JumpTableIndex operand.

bool isGlobal() const

isGlobal - Tests if this is a MO_GlobalAddress operand.

MachineOperandType getType() const

getType - Returns the MachineOperandType for this operand.

getReg - Returns the register number.

@ MO_Immediate

Immediate operand.

@ MO_ConstantPoolIndex

Address of indexed Constant in Constant Pool.

@ MO_GlobalAddress

Address of a global value.

@ MO_MachineBasicBlock

MachineBasicBlock reference.

@ MO_Register

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

StringRef - Represent a constant reference to a string, i.e.

std::string str() const

str - Get the contents as an std::string.

const Triple & getTargetTriple() const

const MCSubtargetInfo * getMCSubtargetInfo() const

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

bool isOSBinFormatELF() const

Tests whether the OS uses the ELF binary format.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

size_t bundleSize(MCInst const &MCI)

void setS27_2_reloc(MCExpr const &Expr, bool Val=true)

void setMemReorderDisabled(MCInst &MCI)

bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)

void setMustNotExtend(MCExpr const &Expr, bool Val=true)

This is an optimization pass for GlobalISel generic memory operations.

@ Low

Lower the current thread's priority such that it does not affect foreground tasks significantly.

Target & getTheHexagonTarget()

std::pair< MCSection *, uint32_t > MCSectionSubPair

void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, MCInst &MCB, HexagonAsmPrinter &AP)

@ MCSA_Global

.type _foo, @gnu_unique_object

This struct is a compact representation of a valid (non-zero power of two) alignment.

RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...