HexagonAsmPrinter.cpp Source File (original) (raw)

50#include

51#include

52#include

54using namespace llvm;

56namespace llvm {

61}

63#define DEBUG_TYPE "asm-printer"

79 default:

83 return;

86 return;

89 return;

92 return;

95 return;

96 }

97}

100

101

102

103

104

107 if (MBB->hasAddressTaken())

108 return false;

110}

111

112

114 const char *ExtraCode,

116

117 if (ExtraCode && ExtraCode[0]) {

118 if (ExtraCode[1] != 0)

119 return true;

120

121 switch (ExtraCode[0]) {

122 default:

123

125 case 'L':

126 case 'H': {

131 return true;

133

134 if (Hexagon::DoubleRegsRegClass.contains(RegNumber))

135 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?

136 Hexagon::isub_lo :

137 Hexagon::isub_hi);

139 return false;

140 }

141 case 'I':

142

143

144 if (MI->getOperand(OpNo).isImm())

145 OS << "i";

146 return false;

147 }

148 }

149

151 return false;

152}

153

155 unsigned OpNo,

156 const char *ExtraCode,

158 if (ExtraCode && ExtraCode[0])

159 return true;

160

163

164 if (Base.isReg())

166 else

168

169 if (Offset.isImm()) {

171 O << "+#" << Offset.getImm();

172 } else {

174 }

175

176 return false;

177}

178

184 if (Imm.getExpr()->evaluateAsAbsolute(Value)) {

186 std::string ImmString;

188 if (AlignSize == 8) {

189 Name = ".CONST_0000000000000000";

190 sectionPrefix = ".gnu.linkonce.l8";

192 } else {

193 Name = ".CONST_00000000";

194 sectionPrefix = ".gnu.linkonce.l4";

196 }

197

198 std::string symbolName =

199 Name.drop_back(ImmString.size()).str() + ImmString;

200 std::string sectionName = sectionPrefix.str() + symbolName;

201

205

212 }

213 } else {

214 assert(Imm.isExpr() && "Expected expression and found none");

217 MCSymbol *MOSymbol = nullptr;

220 else if (MO.isCPI())

222 else if (MO.isJTI())

224 else

226

228 std::string LitaName = ".CONST_" + SymbolName.str();

229

232

238 OutStreamer.emitValue(Imm.getExpr(), AlignSize);

240 }

241 }

242 return Sym;

243}

244

246 unsigned VectorSize, MCContext &Ctx) {

249 for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {

250 if (i != OpNo) {

252 continue;

253 }

260 }

261 return T;

262}

263

266 MCInst &MappedInst = static_cast <MCInst &>(Inst);

270 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;

271

273 default:

274 return;

275

276 case Hexagon::A2_iconst: {

277 Inst.setOpcode(Hexagon::A2_addi);

286 break;

287 }

288

289 case Hexagon::A2_tfrf: {

291 Inst.setOpcode(Hexagon::A2_paddif);

293 break;

294 }

295

296 case Hexagon::A2_tfrt: {

298 Inst.setOpcode(Hexagon::A2_paddit);

300 break;

301 }

302

303 case Hexagon::A2_tfrfnew: {

305 Inst.setOpcode(Hexagon::A2_paddifnew);

307 break;

308 }

309

310 case Hexagon::A2_tfrtnew: {

312 Inst.setOpcode(Hexagon::A2_padditnew);

314 break;

315 }

316

317 case Hexagon::A2_zxtb: {

319 Inst.setOpcode(Hexagon::A2_andir);

321 break;

322 }

323

324

325 case Hexagon::CONST64:

329

332

333 OutStreamer->switchSection(Current.first, Current.second);

336 TmpInst.setOpcode(Hexagon::L2_loadrdgp);

340 MappedInst = TmpInst;

341

342 }

343 break;

344 case Hexagon::CONST32:

350 OutStreamer->switchSection(Current.first, Current.second);

353 TmpInst.setOpcode(Hexagon::L2_loadrigp);

357 MappedInst = TmpInst;

358 }

359 break;

360

361

362

363

364 case Hexagon::C2_pxfer_map: {

366 MappedInst.setOpcode(Hexagon::C2_or);

368 return;

369 }

370

371

372

373

374 case Hexagon::M2_vrcmpys_acc_s1: {

376 assert(Rt.isReg() && "Expected register and none was found");

378 if (Reg & 1)

379 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);

380 else

381 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);

383 return;

384 }

385 case Hexagon::M2_vrcmpys_s1: {

387 assert(Rt.isReg() && "Expected register and none was found");

389 if (Reg & 1)

390 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);

391 else

392 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);

394 return;

395 }

396

397 case Hexagon::M2_vrcmpys_s1rp: {

399 assert(Rt.isReg() && "Expected register and none was found");

401 if (Reg & 1)

402 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);

403 else

404 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);

406 return;

407 }

408

409 case Hexagon::A4_boundscheck: {

411 assert(Rs.isReg() && "Expected register and none was found");

413 if (Reg & 1)

414 MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);

415 else

416 MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);

418 return;

419 }

420

421 case Hexagon::PS_call_nr:

422 Inst.setOpcode(Hexagon::J2_call);

423 break;

424

425 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {

427 int64_t Imm;

429 bool Success = Expr->evaluateAsAbsolute(Imm);

430 assert(Success && "Expected immediate and none was found");

433 if (Imm == 0) {

434 TmpInst.setOpcode(Hexagon::S2_vsathub);

437 MappedInst = TmpInst;

438 return;

439 }

440 TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);

447 MappedInst = TmpInst;

448 return;

449 }

450

451 case Hexagon::S5_vasrhrnd_goodsyntax:

452 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {

455 int64_t Imm;

456 bool Success = Expr->evaluateAsAbsolute(Imm);

457 assert(Success && "Expected immediate and none was found");

460 if (Imm == 0) {

461 TmpInst.setOpcode(Hexagon::A2_combinew);

466

469 MappedInst = TmpInst;

470 return;

471 }

472

473 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)

474 TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);

475 else

476 TmpInst.setOpcode(Hexagon::S5_vasrhrnd);

483 MappedInst = TmpInst;

484 return;

485 }

486

487

488 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {

491 int64_t Imm;

492 bool Success = Expr->evaluateAsAbsolute(Imm);

493 assert(Success && "Expected immediate and none was found");

496 if (Imm == 0) {

497 TmpInst.setOpcode(Hexagon::A2_tfr);

500 MappedInst = TmpInst;

501 return;

502 }

503 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);

510 MappedInst = TmpInst;

511 return;

512 }

513

514

515 case Hexagon::A2_tfrpi: {

519

520 TmpInst.setOpcode(Hexagon::A2_combineii);

522 int64_t Imm;

523 bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);

524 if (Success && Imm < 0) {

528 } else {

532 }

534 MappedInst = TmpInst;

535 return;

536 }

537

538

539 case Hexagon::A2_tfrp: {

544

546 MappedInst.setOpcode(Hexagon::A2_combinew);

547 return;

548 }

549

550 case Hexagon::A2_tfrpt:

551 case Hexagon::A2_tfrpf: {

556

559 ? Hexagon::C2_ccombinewt

560 : Hexagon::C2_ccombinewf);

561 return;

562 }

563

564 case Hexagon::A2_tfrptnew:

565 case Hexagon::A2_tfrpfnew: {

570

573 ? Hexagon::C2_ccombinewnewt

574 : Hexagon::C2_ccombinewnewf);

575 return;

576 }

577

578 case Hexagon::M2_mpysmi: {

580 MCExpr const *Expr = Imm.getExpr();

582 bool Success = Expr->evaluateAsAbsolute(Value);

586 MappedInst.setOpcode(Hexagon::M2_mpysin);

589 } else

590 MappedInst.setOpcode(Hexagon::M2_mpysip);

591 return;

592 }

593

594 case Hexagon::A2_addsp: {

596 assert(Rt.isReg() && "Expected register and none was found");

598 if (Reg & 1)

599 MappedInst.setOpcode(Hexagon::A2_addsph);

600 else

601 MappedInst.setOpcode(Hexagon::A2_addspl);

603 return;

604 }

605

606 case Hexagon::V6_vd0: {

609 "Expected register and none was found");

610

611 TmpInst.setOpcode(Hexagon::V6_vxor);

615 MappedInst = TmpInst;

616 return;

617 }

618

619 case Hexagon::V6_vdd0: {

622 "Expected register and none was found");

623

624 TmpInst.setOpcode(Hexagon::V6_vsubw_dv);

628 MappedInst = TmpInst;

629 return;

630 }

631

632 case Hexagon::V6_vL32Ub_pi:

633 case Hexagon::V6_vL32b_cur_pi:

634 case Hexagon::V6_vL32b_nt_cur_pi:

635 case Hexagon::V6_vL32b_pi:

636 case Hexagon::V6_vL32b_nt_pi:

637 case Hexagon::V6_vL32b_nt_tmp_pi:

638 case Hexagon::V6_vL32b_tmp_pi:

640 return;

641

642 case Hexagon::V6_vL32Ub_ai:

643 case Hexagon::V6_vL32b_ai:

644 case Hexagon::V6_vL32b_cur_ai:

645 case Hexagon::V6_vL32b_nt_ai:

646 case Hexagon::V6_vL32b_nt_cur_ai:

647 case Hexagon::V6_vL32b_nt_tmp_ai:

648 case Hexagon::V6_vL32b_tmp_ai:

650 return;

651

652 case Hexagon::V6_vS32Ub_pi:

653 case Hexagon::V6_vS32b_new_pi:

654 case Hexagon::V6_vS32b_nt_new_pi:

655 case Hexagon::V6_vS32b_nt_pi:

656 case Hexagon::V6_vS32b_pi:

658 return;

659

660 case Hexagon::V6_vS32Ub_ai:

661 case Hexagon::V6_vS32b_ai:

662 case Hexagon::V6_vS32b_new_ai:

663 case Hexagon::V6_vS32b_nt_ai:

664 case Hexagon::V6_vS32b_nt_new_ai:

666 return;

667

668 case Hexagon::V6_vL32b_cur_npred_pi:

669 case Hexagon::V6_vL32b_cur_pred_pi:

670 case Hexagon::V6_vL32b_npred_pi:

671 case Hexagon::V6_vL32b_nt_cur_npred_pi:

672 case Hexagon::V6_vL32b_nt_cur_pred_pi:

673 case Hexagon::V6_vL32b_nt_npred_pi:

674 case Hexagon::V6_vL32b_nt_pred_pi:

675 case Hexagon::V6_vL32b_nt_tmp_npred_pi:

676 case Hexagon::V6_vL32b_nt_tmp_pred_pi:

677 case Hexagon::V6_vL32b_pred_pi:

678 case Hexagon::V6_vL32b_tmp_npred_pi:

679 case Hexagon::V6_vL32b_tmp_pred_pi:

681 return;

682

683 case Hexagon::V6_vL32b_cur_npred_ai:

684 case Hexagon::V6_vL32b_cur_pred_ai:

685 case Hexagon::V6_vL32b_npred_ai:

686 case Hexagon::V6_vL32b_nt_cur_npred_ai:

687 case Hexagon::V6_vL32b_nt_cur_pred_ai:

688 case Hexagon::V6_vL32b_nt_npred_ai:

689 case Hexagon::V6_vL32b_nt_pred_ai:

690 case Hexagon::V6_vL32b_nt_tmp_npred_ai:

691 case Hexagon::V6_vL32b_nt_tmp_pred_ai:

692 case Hexagon::V6_vL32b_pred_ai:

693 case Hexagon::V6_vL32b_tmp_npred_ai:

694 case Hexagon::V6_vL32b_tmp_pred_ai:

696 return;

697

698 case Hexagon::V6_vS32Ub_npred_pi:

699 case Hexagon::V6_vS32Ub_pred_pi:

700 case Hexagon::V6_vS32b_new_npred_pi:

701 case Hexagon::V6_vS32b_new_pred_pi:

702 case Hexagon::V6_vS32b_npred_pi:

703 case Hexagon::V6_vS32b_nqpred_pi:

704 case Hexagon::V6_vS32b_nt_new_npred_pi:

705 case Hexagon::V6_vS32b_nt_new_pred_pi:

706 case Hexagon::V6_vS32b_nt_npred_pi:

707 case Hexagon::V6_vS32b_nt_nqpred_pi:

708 case Hexagon::V6_vS32b_nt_pred_pi:

709 case Hexagon::V6_vS32b_nt_qpred_pi:

710 case Hexagon::V6_vS32b_pred_pi:

711 case Hexagon::V6_vS32b_qpred_pi:

713 return;

714

715 case Hexagon::V6_vS32Ub_npred_ai:

716 case Hexagon::V6_vS32Ub_pred_ai:

717 case Hexagon::V6_vS32b_new_npred_ai:

718 case Hexagon::V6_vS32b_new_pred_ai:

719 case Hexagon::V6_vS32b_npred_ai:

720 case Hexagon::V6_vS32b_nqpred_ai:

721 case Hexagon::V6_vS32b_nt_new_npred_ai:

722 case Hexagon::V6_vS32b_nt_new_pred_ai:

723 case Hexagon::V6_vS32b_nt_npred_ai:

724 case Hexagon::V6_vS32b_nt_nqpred_ai:

725 case Hexagon::V6_vS32b_nt_pred_ai:

726 case Hexagon::V6_vS32b_nt_qpred_ai:

727 case Hexagon::V6_vS32b_pred_ai:

728 case Hexagon::V6_vS32b_qpred_ai:

730 return;

731

732

733 case Hexagon::V6_vS32b_srls_ai:

735 return;

736

737 case Hexagon::V6_vS32b_srls_pi:

739 return;

740 }

741}

742

743

745 Hexagon_MC::verifyInstructionPredicates(MI->getOpcode(),

747

751 const MCInstrInfo &MCII = *Subtarget->getInstrInfo();

752

753 if (MI->isBundle()) {

756

757 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)

758 if (!MII->isDebugInstr() && !MII->isImplicitDef())

760 } else {

762 }

763

765 const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();

766 if (MI->isBundle() && HII.getBundleNoShuf(*MI))

768

771 MCB, nullptr);

772 assert(Ok); (void)Ok;

774 return;

776}

777

779 if (TM.getTargetTriple().isOSBinFormatELF())

780 emitAttributes();

781}

782

786 if (TM.getTargetTriple().isOSBinFormatELF())

788}

789

790void HexagonAsmPrinter::emitAttributes() {

794}

795

797 static const int8_t NoopsInSledCount = 4;

798

799

800

801

802

803

804

805

806

807

808

809

810

811

812

813

814

815

816

817

818

819

820 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);

822

824 SledJump->setOpcode(Hexagon::J2_jump);

825 auto PostSled = OutContext.createTempSymbol();

828

829

830 MCInst SledJumpPacket;

831 SledJumpPacket.setOpcode(Hexagon::BUNDLE);

834

836

837

838

840

843}

844

848

852

856

858

860 "Hexagon Assembly Printer", false, false)

861

863LLVMInitializeHexagonAsmPrinter() {

865}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define LLVM_EXTERNAL_VISIBILITY

static MCSymbol * smallData(AsmPrinter &AP, const MachineInstr &MI, MCStreamer &OutStreamer, const MCOperand &Imm, int AlignSize, const MCSubtargetInfo &STI)

Definition HexagonAsmPrinter.cpp:179

static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo, unsigned VectorSize, MCContext &Ctx)

Definition HexagonAsmPrinter.cpp:245

static unsigned getHexagonRegisterPair(unsigned Reg, const MCRegisterInfo *RI)

Definition HexagonAsmPrinter.cpp:66

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

This class is intended to be used as a driving class for all asm writers.

MCSymbol * getSymbol(const GlobalValue *GV) const

void emitNops(unsigned N)

Emit N NOP instructions.

void EmitToStreamer(MCStreamer &S, const MCInst &Inst)

TargetMachine & TM

Target machine description.

virtual MCSymbol * GetCPISymbol(unsigned CPID) const

Return the symbol for the specified constant pool entry.

virtual void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &OS)

Print the MachineOperand as a symbol.

const MCAsmInfo * MAI

Target Asm Printer information.

MachineFunction * MF

The current machine function.

virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const

Return true if the basic block has exactly one predecessor and the control transfer mechanism between...

MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const

Return the symbol for the specified jump table entry.

void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)

MCContext & OutContext

This is the context for the output file that we are streaming.

std::unique_ptr< MCStreamer > OutStreamer

This is the MCStreamer object for the file we are generating.

const MCSubtargetInfo & getSubtargetInfo() const

Return information about subtarget.

virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)

Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.

void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)

Definition HexagonAsmPrinter.cpp:845

void EmitSled(const MachineInstr &MI, SledKind Kind)

Definition HexagonAsmPrinter.cpp:796

void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)

Definition HexagonAsmPrinter.cpp:849

bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override

Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...

Definition HexagonAsmPrinter.cpp:154

bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override

Return true if the basic block has exactly one predecessor and the control transfer mechanism between...

Definition HexagonAsmPrinter.cpp:105

bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override

PrintAsmOperand - Print out an operand for an inline asm expression.

Definition HexagonAsmPrinter.cpp:113

void emitInstruction(const MachineInstr *MI) override

Print out a single Hexagon MI to the current output stream.

Definition HexagonAsmPrinter.cpp:744

void emitEndOfAsmFile(Module &M) override

This virtual method can be overridden by targets that want to emit something at the end of their file...

Definition HexagonAsmPrinter.cpp:783

void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)

Definition HexagonAsmPrinter.cpp:853

void emitStartOfAsmFile(Module &M) override

This virtual method can be overridden by targets that want to emit something at the start of their fi...

Definition HexagonAsmPrinter.cpp:778

void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)

Definition HexagonAsmPrinter.cpp:74

void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB)

Definition HexagonAsmPrinter.cpp:264

static char const * getRegisterName(MCRegister Reg)

static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)

void emitTargetAttributes(const MCSubtargetInfo &STI)

virtual void finishAttributeSection()

static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)

LLVM_ABI MCSymbol * getOrCreateSymbol(const Twine &Name)

Lookup the symbol inside with the specified Name.

Base class for the full range of assembler expressions which are needed for parsing.

Instances of this class represent a single low-level machine instruction.

unsigned getNumOperands() const

unsigned getOpcode() const

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

Interface to description of machine instruction set.

Instances of this class represent operands of the MCInst class.

static MCOperand createExpr(const MCExpr *Val)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

void setReg(MCRegister Reg)

Set the register number.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

static MCOperand createInst(const MCInst *Val)

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

iterator_range< MCSuperRegIterator > superregs(MCRegister Reg) const

Return an iterator range over all super-registers of Reg, excluding Reg.

uint16_t getEncodingValue(MCRegister Reg) const

Returns the encoding for Reg.

MCRegister getSubReg(MCRegister Reg, unsigned Idx) const

Returns the physical register number of sub-register "Index" for physical register RegNo.

Wrapper class representing physical registers. Should be passed by value.

This represents a section on linux, lots of unix variants and some bare metal systems.

Streaming machine code generation interface.

virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0

Add the given Attribute to Symbol.

MCContext & getContext() const

void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())

virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())

Emit a label for Symbol into the current section.

virtual void emitIntValue(uint64_t Value, unsigned Size)

Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.

virtual void emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit=0)

Emit nops until the byte alignment ByteAlignment is reached.

virtual void switchSection(MCSection *Section, uint32_t Subsec=0)

Set the current section where code is being emitted to Section.

Generic base class for all target subtargets.

static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx, SMLoc Loc=SMLoc())

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

LLVM_ABI void print(raw_ostream &OS, const MCAsmInfo *MAI) const

print - Print the value to the stream OS.

bool isUndefined() const

isUndefined - Check if this symbol undefined (i.e., implicitly defined).

StringRef getName() const

getName - Get the symbol name.

static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())

LLVM_ABI MCSymbol * getSymbol() const

Return the MCSymbol for this basic block.

Instructions::const_iterator const_instr_iterator

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

const GlobalValue * getGlobal() const

bool isReg() const

isReg - Tests if this is a MO_Register operand.

MachineBasicBlock * getMBB() const

bool isCPI() const

isCPI - Tests if this is a MO_ConstantPoolIndex operand.

bool isJTI() const

isJTI - Tests if this is a MO_JumpTableIndex operand.

bool isGlobal() const

isGlobal - Tests if this is a MO_GlobalAddress operand.

MachineOperandType getType() const

getType - Returns the MachineOperandType for this operand.

getReg - Returns the register number.

@ MO_Immediate

Immediate operand.

@ MO_ConstantPoolIndex

Address of indexed Constant in Constant Pool.

@ MO_GlobalAddress

Address of a global value.

@ MO_MachineBasicBlock

MachineBasicBlock reference.

@ MO_Register

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

StringRef - Represent a constant reference to a string, i.e.

std::string str() const

str - Get the contents as an std::string.

const MCSubtargetInfo * getMCSubtargetInfo() const

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

size_t bundleSize(MCInst const &MCI)

void setS27_2_reloc(MCExpr const &Expr, bool Val=true)

void setMemReorderDisabled(MCInst &MCI)

bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)

void setMustNotExtend(MCExpr const &Expr, bool Val=true)

This is an optimization pass for GlobalISel generic memory operations.

@ Low

Lower the current thread's priority such that it does not affect foreground tasks significantly.

FunctionAddr VTableAddr Value

std::string utohexstr(uint64_t X, bool LowerCase=false, unsigned Width=0)

Target & getTheHexagonTarget()

void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, MCInst &MCB, HexagonAsmPrinter &AP)

@ Success

The lock was released successfully.

@ Sub

Subtraction of integers.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

std::pair< MCSection *, uint32_t > MCSectionSubPair

@ MCSA_Global

.type _foo, @gnu_unique_object

This struct is a compact representation of a valid (non-zero power of two) alignment.

RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...