HexagonCopyToCombine.cpp Source File (original) (raw)

32using namespace llvm;

34#define DEBUG_TYPE "hexagon-copy-combine"

39 cl::desc("Disable merging into combines"));

43 cl::desc("Disable generation of const64"));

44static

48 cl::desc("Maximum distance between a tfr feeding a store we "

49 "consider the store still to be newifiable"));

51namespace {

62public:

63 static char ID;

67 void getAnalysisUsage(AnalysisUsage &AU) const override {

69 }

71 StringRef getPassName() const override {

72 return "Hexagon Copy-To-Combine Pass";

73 }

75 bool runOnMachineFunction(MachineFunction &Fn) override;

77 MachineFunctionProperties getRequiredProperties() const override {

78 return MachineFunctionProperties().setNoVRegs();

79 }

81private:

82 MachineInstr *findPairable(MachineInstr &I1, bool &DoInsertAtI1,

83 bool AllowC64);

85 void findPotentialNewifiableTFRs(MachineBasicBlock &);

87 void combine(MachineInstr &I1, MachineInstr &I2,

89 bool OptForSize);

91 bool isSafeToMoveTogether(MachineInstr &I1, MachineInstr &I2,

92 unsigned I1DestReg, unsigned I2DestReg,

93 bool &DoInsertAtI1);

96 MachineOperand &HiOperand, MachineOperand &LoOperand);

99 MachineOperand &HiOperand, MachineOperand &LoOperand);

100

102 MachineOperand &HiOperand, MachineOperand &LoOperand);

103

105 MachineOperand &HiOperand, MachineOperand &LoOperand);

106

108 MachineOperand &HiOperand, MachineOperand &LoOperand);

109};

110

111}

112

113char HexagonCopyToCombine::ID = 0;

114

116 "Hexagon Copy-To-Combine Pass", false, false)

117

120 switch (MI.getOpcode()) {

121 case Hexagon::A2_tfr: {

122

123 const MachineOperand &Op0 = MI.getOperand(0);

124 const MachineOperand &Op1 = MI.getOperand(1);

125 assert(Op0.isReg() && Op1.isReg());

126

127 Register DestReg = Op0.getReg();

128 Register SrcReg = Op1.getReg();

129 return Hexagon::IntRegsRegClass.contains(DestReg) &&

130 Hexagon::IntRegsRegClass.contains(SrcReg);

131 }

132

133 case Hexagon::A2_tfrsi: {

134

135

136 const MachineOperand &Op0 = MI.getOperand(0);

137 const MachineOperand &Op1 = MI.getOperand(1);

138 assert(Op0.isReg());

139

140 Register DestReg = Op0.getReg();

141

142

143

144 if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)

145 return false;

146

147

148 bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm());

149 return Hexagon::IntRegsRegClass.contains(DestReg) &&

150 (ShouldCombineAggressively || NotExt);

151 }

152

153 case Hexagon::V6_vassign:

154 return true;

155

156 default:

157 break;

158 }

159

160 return false;

161}

162

164 if (I.getOpcode() == Hexagon::TFRI64_V4 ||

165 I.getOpcode() == Hexagon::A2_tfrsi) {

167 return .isImm() || isInt<N> (Op.getImm());

168 }

169 return false;

170}

171

172

173

177 unsigned HiOpc = HighRegInst.getOpcode();

178 unsigned LoOpc = LowRegInst.getOpcode();

179

180 auto verifyOpc = [](unsigned Opc) -> void {

181 switch (Opc) {

182 case Hexagon::A2_tfr:

183 case Hexagon::A2_tfrsi:

184 case Hexagon::V6_vassign:

185 break;

186 default:

188 }

189 };

190 verifyOpc(HiOpc);

191 verifyOpc(LoOpc);

192

193 if (HiOpc == Hexagon::V6_vassign || LoOpc == Hexagon::V6_vassign)

194 return HiOpc == LoOpc;

195

196 if (!AllowC64) {

197

200 return false;

201 }

202

203

204

209

210

211

214 return false;

215

216 return true;

217}

218

221 if (Hexagon::IntRegsRegClass.contains(Reg))

222 return (Reg - Hexagon::R0) % 2 == 0;

223 if (Hexagon::HvxVRRegClass.contains(Reg))

224 return (Reg - Hexagon::V0) % 2 == 0;

226}

227

230 if (Op.isReg() && Op.getReg() == RegNotKilled && Op.isKill())

231 Op.setIsKill(false);

232}

233

234

235

237 unsigned DestReg,

240 MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||

241 MI.hasUnmodeledSideEffects() || MI.isInlineAsm() ||

242 MI.isMetaInstruction();

243}

244

248

249

250

251bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1,

253 unsigned I1DestReg,

254 unsigned I2DestReg,

255 bool &DoInsertAtI1) {

257

258

259

260 if (I2UseReg && I1.modifiesRegister(I2UseReg, TRI))

261 return false;

262

263 bool isSafe = true;

264

265

266 {

267

268

269

272

274 End = ++I1.getIterator().getReverse();

275

276

277

278 unsigned KilledOperand = 0;

280 KilledOperand = I2UseReg;

281 MachineInstr *KillingInstr = nullptr;

282

283 for (; I != End; ++I) {

284

285

286

287

288

289

290 if (I->isDebugInstr())

291 continue;

292

294 isSafe = false;

295 break;

296 }

297

298

299 if (!KillingInstr && KilledOperand &&

300 I->readsRegister(KilledOperand, TRI))

301 KillingInstr = &*I;

302 }

303 if (isSafe) {

304

305 if (KillingInstr) {

307 (void)Added;

308 assert(Added && "Must successfully update kill flag");

310 }

311 DoInsertAtI1 = true;

312 return true;

313 }

314 }

315

316

317 {

318

320

324

325

326

327 MachineInstr *KillingInstr = nullptr;

328 unsigned KilledOperand = 0;

329

330 while(++I != End) {

331 MachineInstr &MI = *I;

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348 if (MI.isDebugInstr()) {

349 if (MI.readsRegister(I1DestReg, TRI))

351 continue;

352 }

353

355

356 (.killsRegister(I1UseReg, nullptr) &&

357 MI.killsRegister(I1UseReg, TRI)))

358 return false;

359

360

361 if (I1UseReg && MI.killsRegister(I1UseReg, nullptr)) {

362 assert(!KillingInstr && "Should only see one killing instruction");

363 KilledOperand = I1UseReg;

364 KillingInstr = &MI;

365 }

366 }

367 if (KillingInstr) {

369

370

371 bool Added = I1.addRegisterKilled(KilledOperand, TRI);

372 (void)Added;

373 assert(Added && "Must successfully update kill flag");

374 }

375 DoInsertAtI1 = false;

376 }

377

378 return true;

379}

380

381

382

383void

384HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {

385 DenseMap<unsigned, MachineInstr *> LastDef;

386 for (MachineInstr &MI : BB) {

387 if (MI.isDebugInstr())

388 continue;

389

390

391 if (TII->mayBeNewStore(MI)) {

392

393 for (const MachineOperand &Op : MI.operands()) {

394

395 if (.isReg() || .isUse() || .getReg())

396 continue;

397

398

400 MachineInstr *DefInst = LastDef[Reg];

401 if (!DefInst)

402 continue;

404 continue;

405

406

407

409 unsigned NumInstsToDef = 0;

410 while (&*It != &MI) {

411 if (!It->isDebugInstr())

412 ++NumInstsToDef;

413 ++It;

414 }

415

417 continue;

418

419 PotentiallyNewifiableTFR.insert(DefInst);

420 }

421

422 continue;

423 }

424

425

426

427 for (MachineOperand &Op : MI.operands()) {

428 if (Op.isReg()) {

429 if (.isDef() || .getReg())

430 continue;

432 if (Hexagon::DoubleRegsRegClass.contains(Reg)) {

435 } else if (Hexagon::IntRegsRegClass.contains(Reg))

436 LastDef[Reg] = &MI;

437 } else if (Op.isRegMask()) {

438 for (unsigned Reg : Hexagon::IntRegsRegClass)

439 if (Op.clobbersPhysReg(Reg))

440 LastDef[Reg] = &MI;

441 }

442 }

443 }

444}

445

446bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {

448 return false;

449

451

452 bool HasChanged = false;

453

454

458

461

462

465

466

469

470

471 for (MachineBasicBlock &MBB : MF) {

472 PotentiallyNewifiableTFR.clear();

473 findPotentialNewifiableTFRs(MBB);

474

475

477 MI != End;) {

478 MachineInstr &I1 = *MI++;

479

480 if (I1.isDebugInstr())

481 continue;

482

483

484

485

487 continue;

488

489

491 continue;

492

493

494

495

496 bool DoInsertAtI1 = false;

497 DbgMItoMove.clear();

498 MachineInstr *I2 = findPairable(I1, DoInsertAtI1, OptForSize);

499 if (I2) {

500 HasChanged = true;

501 combine(I1, *I2, MI, DoInsertAtI1, OptForSize);

502 }

503 }

504 }

505

506 return HasChanged;

507}

508

509

510

511

512

513MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,

514 bool &DoInsertAtI1,

515 bool AllowC64) {

517 while (I2 != I1.getParent()->end() && I2->isDebugInstr())

518 ++I2;

519

520 Register I1DestReg = I1.getOperand(0).getReg();

521

523 ++I2) {

524

525 if (I2->modifiesRegister(I1DestReg, TRI))

526 break;

527

528

530 continue;

531

532

534 continue;

535

536 Register I2DestReg = I2->getOperand(0).getReg();

537

538

539

540 bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;

541 bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;

542 unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;

543 if ((!IsI1LowReg && !IsI2LowReg) || isEvenReg (FirstRegIndex))

544 continue;

545

546

547

548

551 break;

552

553 if (isSafeToMoveTogether(I1, *I2, I1DestReg, I2DestReg, DoInsertAtI1))

554 return &*I2;

555

556

557 break;

558 }

559 return nullptr;

560}

561

562void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2,

564 bool DoInsertAtI1, bool OptForSize) {

565

566

568 ++MI;

569

570

571 Register I1DestReg = I1.getOperand(0).getReg();

573 bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;

574 unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;

575 unsigned SubLo;

576

577 const TargetRegisterClass *SuperRC = nullptr;

578 if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {

579 SuperRC = &Hexagon::DoubleRegsRegClass;

580 SubLo = Hexagon::isub_lo;

581 } else if (Hexagon::HvxVRRegClass.contains(LoRegDef)) {

583 SuperRC = &Hexagon::HvxWRRegClass;

584 SubLo = Hexagon::vsub_lo;

585 } else

587

588

589 MCRegister DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);

590 assert(DoubleRegDest.isValid() && "Expect a valid register");

591

592

593 MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1);

594 MachineOperand &HiOperand = IsI1Loreg ? I2.getOperand(1) : I1.getOperand(1);

595

596

597 bool IsHiReg = HiOperand.isReg();

598 bool IsLoReg = LoOperand.isReg();

599

600

601 bool IsC64 = OptForSize && LoOperand.isImm() && HiOperand.isImm() &&

603

605

606 if (IsHiReg && IsLoReg)

607 emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);

608 else if (IsHiReg)

609 emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);

610 else if (IsLoReg)

611 emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);

613 emitConst64(InsertPt, DoubleRegDest, HiOperand, LoOperand);

614 else

615 emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);

616

617

618

619 if (!DoInsertAtI1 && DbgMItoMove.size() != 0) {

620

621 MachineBasicBlock *BB = InsertPt->getParent();

622 for (auto *NewMI : DbgMItoMove) {

623

624

625 if (NewMI == MI)

626 ++MI;

627 BB->splice(InsertPt, BB, NewMI);

628 }

629 }

630

631 I1.eraseFromParent();

633}

634

636 unsigned DoubleDestReg,

637 MachineOperand &HiOperand,

638 MachineOperand &LoOperand) {

640

641 DebugLoc DL = InsertPt->getDebugLoc();

642 MachineBasicBlock *BB = InsertPt->getParent();

644 "Both operands must be immediate");

645

646 int64_t V = HiOperand.getImm();

647 V = (V << 32) | (0x0ffffffffLL & LoOperand.getImm());

648 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::CONST64), DoubleDestReg)

650}

651

653 unsigned DoubleDestReg,

654 MachineOperand &HiOperand,

655 MachineOperand &LoOperand) {

656 DebugLoc DL = InsertPt->getDebugLoc();

657 MachineBasicBlock *BB = InsertPt->getParent();

658

659

661 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)

665 return;

666 }

668 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)

672 return;

673 }

674

675

677 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)

681 return;

682 }

684 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)

688 return;

689 }

690

691

692 if (HiOperand.isJTI()) {

693 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)

696 return;

697 }

698 if (LoOperand.isJTI()) {

699 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)

702 return;

703 }

704

705

706 if (HiOperand.isCPI()) {

707 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)

711 return;

712 }

713 if (LoOperand.isCPI()) {

714 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)

718 return;

719 }

720

721

722

723

725 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)

728 return;

729 }

730

731

733 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)

736 return;

737 }

738

739

740

741 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)

744}

745

747 unsigned DoubleDestReg,

748 MachineOperand &HiOperand,

749 MachineOperand &LoOperand) {

752

753 DebugLoc DL = InsertPt->getDebugLoc();

754 MachineBasicBlock *BB = InsertPt->getParent();

755

756

758 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)

761 .addReg(LoReg, LoRegKillFlag);

762 return;

763 }

764

766 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)

769 .addReg(LoReg, LoRegKillFlag);

770 return;

771 }

772

773 if (HiOperand.isJTI()) {

774 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)

776 .addReg(LoReg, LoRegKillFlag);

777 return;

778 }

779

780 if (HiOperand.isCPI()) {

781 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)

784 .addReg(LoReg, LoRegKillFlag);

785 return;

786 }

787

788

789 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)

791 .addReg(LoReg, LoRegKillFlag);

792}

793

795 unsigned DoubleDestReg,

796 MachineOperand &HiOperand,

797 MachineOperand &LoOperand) {

800

801 DebugLoc DL = InsertPt->getDebugLoc();

802 MachineBasicBlock *BB = InsertPt->getParent();

803

804

806 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)

807 .addReg(HiReg, HiRegKillFlag)

810 return;

811 }

812

814 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)

815 .addReg(HiReg, HiRegKillFlag)

818 return;

819 }

820

821 if (LoOperand.isJTI()) {

822 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)

825 return;

826 }

827

828 if (LoOperand.isCPI()) {

829 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)

833 return;

834 }

835

836

837

838 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)

839 .addReg(HiReg, HiRegKillFlag)

841}

842

844 unsigned DoubleDestReg,

845 MachineOperand &HiOperand,

846 MachineOperand &LoOperand) {

851

852 DebugLoc DL = InsertPt->getDebugLoc();

853 MachineBasicBlock *BB = InsertPt->getParent();

854

855

856

857 unsigned NewOpc;

858 if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) {

859 NewOpc = Hexagon::A2_combinew;

860 } else if (Hexagon::HvxWRRegClass.contains(DoubleDestReg)) {

862 NewOpc = Hexagon::V6_vcombine;

863 } else

865

866 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)

867 .addReg(HiReg, HiRegKillFlag)

868 .addReg(LoReg, LoRegKillFlag);

869}

870

872 return new HexagonCopyToCombine();

873}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file defines the DenseMap class.

This file defines the DenseSet and SmallDenseSet classes.

static Register UseReg(const MachineOperand &MO)

Definition HexagonCopyToCombine.cpp:245

static cl::opt< bool > IsConst64Disabled("disable-const64", cl::Hidden, cl::desc("Disable generation of const64"))

static bool isEvenReg(unsigned Reg)

Definition HexagonCopyToCombine.cpp:219

static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, unsigned DestReg, const TargetRegisterInfo *TRI)

Returns true if it is unsafe to move a copy instruction from UseReg to DestReg over the instruction M...

Definition HexagonCopyToCombine.cpp:236

static cl::opt< bool > IsCombinesDisabled("disable-merge-into-combines", cl::Hidden, cl::desc("Disable merging into combines"))

const HexagonInstrInfo bool ShouldCombineAggressively

Definition HexagonCopyToCombine.cpp:119

static bool areCombinableOperations(const TargetRegisterInfo *TRI, MachineInstr &HighRegInst, MachineInstr &LowRegInst, bool AllowC64)

areCombinableOperations - Returns true if the two instruction can be merge into a combine (ignoring r...

Definition HexagonCopyToCombine.cpp:174

static cl::opt< unsigned > MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store", cl::Hidden, cl::init(4), cl::desc("Maximum distance between a tfr feeding a store we " "consider the store still to be newifiable"))

static void removeKillInfo(MachineInstr &MI, unsigned RegNotKilled)

Definition HexagonCopyToCombine.cpp:228

static bool isGreaterThanNBitTFRI(const MachineInstr &I)

Definition HexagonCopyToCombine.cpp:163

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

Implements a dense probed hash-table based set.

FunctionPass class - This class is used to implement most global optimizations.

bool hasOptSize() const

Optimize this function for size (-Os) or minimum size (-Oz).

const HexagonInstrInfo * getInstrInfo() const override

const HexagonRegisterInfo * getRegisterInfo() const override

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

constexpr bool isValid() const

MachineInstrBundleIterator< MachineInstr, true > reverse_iterator

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

MachineInstrBundleIterator< MachineInstr > iterator

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Function & getFunction()

Return the LLVM function that this machine code represents.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const

Return true if the MachineInstr kills the specified register.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

LLVM_ABI bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI kills a register.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

const GlobalValue * getGlobal() const

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isCPI() const

isCPI - Tests if this is a MO_ConstantPoolIndex operand.

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

bool isJTI() const

isJTI - Tests if this is a MO_JumpTableIndex operand.

const BlockAddress * getBlockAddress() const

unsigned getTargetFlags() const

bool isGlobal() const

isGlobal - Tests if this is a MO_GlobalAddress operand.

bool isBlockAddress() const

isBlockAddress - Tests if this is a MO_BlockAddress operand.

getReg - Returns the register number.

int64_t getOffset() const

Return the offset from the symbol in this operand.

Wrapper class representing virtual and physical registers.

static constexpr bool isPhysicalRegister(unsigned Reg)

Return true if the specified register number is in the physical register namespace.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

CodeGenOptLevel getOptLevel() const

Returns the optimization level: None, Less, Default, or Aggressive.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

std::pair< iterator, bool > insert(const ValueT &V)

size_type count(const_arg_type_t< ValueT > V) const

Return 1 if the specified key is in the set, 0 otherwise.

self_iterator getIterator()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

FunctionPass * createHexagonCopyToCombine()

Definition HexagonCopyToCombine.cpp:871

unsigned getKillRegState(bool B)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op