LLVM: lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Source File (original) (raw)

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29#include

30#include

31#include

32#include

33

34#define DEBUG_TYPE "hexagon-disassembler"

35

36using namespace llvm;

39

41

42namespace {

43

44

46public:

47 std::unique_ptr const MCII;

48 mutable std::unique_ptr CurrentBundle;

49 mutable MCInst const *CurrentExtender;

50

53 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(nullptr),

54 CurrentExtender(nullptr) {}

55

58 raw_ostream &CStream, bool &Complete) const;

62

66

67 void remapInstruction(MCInst &Instr) const;

68

71 uint64_t Address) const override;

72

73private:

76

77 void resetBundle() const {

78 CurrentBundle.reset();

79 CurrentInstruction = nullptr;

80 }

81

82 mutable MCOperand *CurrentInstruction = nullptr;

83};

84

85static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,

88 if (!Disassembler.CurrentExtender ||

93 int64_t Bits;

95 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(

96 Bits);

100 uint64_t Operand = Upper26 | Lower6;

101 return Operand;

102}

103static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {

104 return *static_cast<HexagonDisassembler const *>(Decoder);

105}

106template <size_t T>

107static void signedDecoder(MCInst &MI, unsigned tmp,

109 HexagonDisassembler const &Disassembler = disassembler(Decoder);

110 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp));

113}

114}

115

116

117

118

172

181

185 return DecodeStatus::Success;

186}

187

191 return DecodeStatus::Success;

192}

193

195#include "HexagonGenDisassemblerTables.inc"

196

200 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());

201}

202

208

212 bool Complete = false;

214

215 CurrentBundle.reset(new MCInst);

216 CurrentBundle->setOpcode(Hexagon::BUNDLE);

218 while (Result == Success && !Complete) {

220 return false;

221 MCInst *Inst = getContext().createMCInst();

222 Result = getSingleInstruction(*Inst, *CurrentBundle, Bytes, Address, CS,

223 Complete);

227 }

229 return false;

231 return false;

232

234 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;

235 HexagonMCChecker Checker(getContext(), *MCII, STI_, *CurrentBundle,

236 *getContext().getRegisterInfo(), false);

237 if (!Checker.check())

238 return false;

239 remapInstruction(*CurrentBundle);

240 return true;

241}

242

243DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

244 ArrayRef<uint8_t> Bytes,

246 raw_ostream &CS) const {

247 CommentStream = &CS;

248

250 uint64_t BytesToSkip = 0;

251

252 if (!CurrentBundle) {

253 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {

254 Size = BytesToSkip;

255 resetBundle();

257 }

258 CurrentInstruction = (CurrentBundle->begin() + 1);

259 }

260

261 MI = *(CurrentInstruction->getInst());

263 if (++CurrentInstruction == CurrentBundle->end())

264 resetBundle();

266}

267

268DecodeStatus HexagonDisassembler::getInstructionBundle(MCInst &MI,

269 uint64_t &Size,

270 ArrayRef<uint8_t> Bytes,

272 raw_ostream &CS) const {

273 CommentStream = &CS;

275 uint64_t BytesToSkip = 0;

276 assert(!CurrentBundle);

277

278 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {

279 Size = BytesToSkip;

280 resetBundle();

282 }

283

284 MI = *CurrentBundle;

286 resetBundle();

287

289}

290

291void HexagonDisassembler::remapInstruction(MCInst &Instr) const {

293 auto &MI = const_cast<MCInst &>(*I.getInst());

294 switch (MI.getOpcode()) {

295 case Hexagon::S2_allocframe:

296 if (MI.getOperand(0).getReg() == Hexagon::R29) {

297 MI.setOpcode(Hexagon::S6_allocframe_to_raw);

298 MI.erase(MI.begin () + 1);

299 MI.erase(MI.begin ());

300 }

301 break;

302 case Hexagon::L2_deallocframe:

303 if (MI.getOperand(0).getReg() == Hexagon::D15 &&

304 MI.getOperand(1).getReg() == Hexagon::R30) {

305 MI.setOpcode(L6_deallocframe_map_to_raw);

306 MI.erase(MI.begin () + 1);

307 MI.erase(MI.begin ());

308 }

309 break;

310 case Hexagon::L4_return:

311 if (MI.getOperand(0).getReg() == Hexagon::D15 &&

312 MI.getOperand(1).getReg() == Hexagon::R30) {

313 MI.setOpcode(L6_return_map_to_raw);

314 MI.erase(MI.begin () + 1);

315 MI.erase(MI.begin ());

316 }

317 break;

318 case Hexagon::L4_return_t:

319 if (MI.getOperand(0).getReg() == Hexagon::D15 &&

320 MI.getOperand(2).getReg() == Hexagon::R30) {

321 MI.setOpcode(L4_return_map_to_raw_t);

322 MI.erase(MI.begin () + 2);

323 MI.erase(MI.begin ());

324 }

325 break;

326 case Hexagon::L4_return_f:

327 if (MI.getOperand(0).getReg() == Hexagon::D15 &&

328 MI.getOperand(2).getReg() == Hexagon::R30) {

329 MI.setOpcode(L4_return_map_to_raw_f);

330 MI.erase(MI.begin () + 2);

331 MI.erase(MI.begin ());

332 }

333 break;

334 case Hexagon::L4_return_tnew_pt:

335 if (MI.getOperand(0).getReg() == Hexagon::D15 &&

336 MI.getOperand(2).getReg() == Hexagon::R30) {

337 MI.setOpcode(L4_return_map_to_raw_tnew_pt);

338 MI.erase(MI.begin () + 2);

339 MI.erase(MI.begin ());

340 }

341 break;

342 case Hexagon::L4_return_fnew_pt:

343 if (MI.getOperand(0).getReg() == Hexagon::D15 &&

344 MI.getOperand(2).getReg() == Hexagon::R30) {

345 MI.setOpcode(L4_return_map_to_raw_fnew_pt);

346 MI.erase(MI.begin () + 2);

347 MI.erase(MI.begin ());

348 }

349 break;

350 case Hexagon::L4_return_tnew_pnt:

351 if (MI.getOperand(0).getReg() == Hexagon::D15 &&

352 MI.getOperand(2).getReg() == Hexagon::R30) {

353 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);

354 MI.erase(MI.begin () + 2);

355 MI.erase(MI.begin ());

356 }

357 break;

358 case Hexagon::L4_return_fnew_pnt:

359 if (MI.getOperand(0).getReg() == Hexagon::D15 &&

360 MI.getOperand(2).getReg() == Hexagon::R30) {

361 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);

362 MI.erase(MI.begin () + 2);

363 MI.erase(MI.begin ());

364 }

365 break;

366 }

367 }

368}

369

370DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,

371 ArrayRef<uint8_t> Bytes,

373 raw_ostream &cs,

374 bool &Complete) const {

376

378

382 if (BundleSize == 0)

384 else if (BundleSize == 1)

386 else

387 return DecodeStatus::Fail;

388 }

389

392

396 unsigned duplexIClass;

397 uint8_t const *DecodeLow, *DecodeHigh;

398 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);

399 switch (duplexIClass) {

400 default:

402 case 0:

403 DecodeLow = DecoderTableSUBINSN_L132;

404 DecodeHigh = DecoderTableSUBINSN_L132;

405 break;

406 case 1:

407 DecodeLow = DecoderTableSUBINSN_L232;

408 DecodeHigh = DecoderTableSUBINSN_L132;

409 break;

410 case 2:

411 DecodeLow = DecoderTableSUBINSN_L232;

412 DecodeHigh = DecoderTableSUBINSN_L232;

413 break;

414 case 3:

415 DecodeLow = DecoderTableSUBINSN_A32;

416 DecodeHigh = DecoderTableSUBINSN_A32;

417 break;

418 case 4:

419 DecodeLow = DecoderTableSUBINSN_L132;

420 DecodeHigh = DecoderTableSUBINSN_A32;

421 break;

422 case 5:

423 DecodeLow = DecoderTableSUBINSN_L232;

424 DecodeHigh = DecoderTableSUBINSN_A32;

425 break;

426 case 6:

427 DecodeLow = DecoderTableSUBINSN_S132;

428 DecodeHigh = DecoderTableSUBINSN_A32;

429 break;

430 case 7:

431 DecodeLow = DecoderTableSUBINSN_S232;

432 DecodeHigh = DecoderTableSUBINSN_A32;

433 break;

434 case 8:

435 DecodeLow = DecoderTableSUBINSN_S132;

436 DecodeHigh = DecoderTableSUBINSN_L132;

437 break;

438 case 9:

439 DecodeLow = DecoderTableSUBINSN_S132;

440 DecodeHigh = DecoderTableSUBINSN_L232;

441 break;

442 case 10:

443 DecodeLow = DecoderTableSUBINSN_S132;

444 DecodeHigh = DecoderTableSUBINSN_S132;

445 break;

446 case 11:

447 DecodeLow = DecoderTableSUBINSN_S232;

448 DecodeHigh = DecoderTableSUBINSN_S132;

449 break;

450 case 12:

451 DecodeLow = DecoderTableSUBINSN_S232;

452 DecodeHigh = DecoderTableSUBINSN_L132;

453 break;

454 case 13:

455 DecodeLow = DecoderTableSUBINSN_S232;

456 DecodeHigh = DecoderTableSUBINSN_L232;

457 break;

458 case 14:

459 DecodeLow = DecoderTableSUBINSN_S232;

460 DecodeHigh = DecoderTableSUBINSN_S232;

461 break;

462 }

463 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);

464 MCInst *MILow = getContext().createMCInst();

465 MCInst *MIHigh = getContext().createMCInst();

466 auto TmpExtender = CurrentExtender;

467 CurrentExtender =

468 nullptr;

469 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,

470 this, STI);

471 CurrentExtender = TmpExtender;

472 if (Result != DecodeStatus::Success)

473 return DecodeStatus::Fail;

474 Result = decodeInstruction(

475 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);

476 if (Result != DecodeStatus::Success)

477 return DecodeStatus::Fail;

480 MI.addOperand(OPLow);

481 MI.addOperand(OPHigh);

482 Complete = true;

483 } else {

486 Complete = true;

487

488 if (CurrentExtender != nullptr)

489 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,

491

493 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,

494 STI);

495

497 STI.hasFeature(Hexagon::ExtensionHVX))

498 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,

500

501 }

502

505 MCOperand &MCO = MI.getOperand(OpIndex);

506 assert(MCO.isReg() && "New value consumers must be registers");

508 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());

510

512 unsigned Lookback = (Register & 0x6) >> 1;

515 bool PrevVector = false;

519 if (i == n)

520

523 if (Vector && !CurrentVector)

524

525 ++Lookback;

527 ++Lookback;

528 PrevVector = CurrentVector;

529 if (Offset == Lookback)

530 break;

531 }

532 auto const &Inst = *i->getInst();

533 bool SubregBit = (Register & 0x1) != 0;

535

537 SubregBit

540 assert(Producer != Hexagon::NoRegister);

541 MCO.setReg(Producer);

545

548 const unsigned ProdPairIndex =

550 if (Rev)

551 SubregBit = !SubregBit;

552 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;

553 } else if (SubregBit)

554

555

557 assert(Producer != Hexagon::NoRegister);

558 MCO.setReg(Producer);

559 } else

561 }

562

563 if (CurrentExtender != nullptr) {

565 ? *MI.getOperand(1).getInst()

566 : MI;

570 }

572}

573

574Expected HexagonDisassembler::onSymbolStart(SymbolInfoTy &Symbol,

575 uint64_t &Size,

576 ArrayRef<uint8_t> Bytes,

577 uint64_t Address) const {

578

579

580

582 resetBundle();

583 return true;

584}

585

588 if (RegNo < Table.size()) {

591 }

592

594}

595

601

606 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,

607 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,

608 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,

609 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,

610 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,

611 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,

612 Hexagon::R30, Hexagon::R31};

613

615}

616

621 static const MCPhysReg GeneralSubRegDecoderTable[] = {

622 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,

623 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,

624 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,

625 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,

626 };

627

629}

630

634 static const MCPhysReg HvxVRDecoderTable[] = {

635 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,

636 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,

637 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,

638 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,

639 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,

640 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,

641 Hexagon::V30, Hexagon::V31};

642

644}

645

650 static const MCPhysReg DoubleRegDecoderTable[] = {

651 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,

652 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,

653 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,

654 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};

655

657}

658

663 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {

664 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,

665 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};

666

667 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);

668}

669

673 static const MCPhysReg HvxWRDecoderTable[] = {

674 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,

675 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,

676 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,

677 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,

678 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,

679 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,

680 Hexagon::W15, Hexagon::WR15,

681 };

682

684}

685

686[[maybe_unused]]

690 static const MCPhysReg HvxVQRDecoderTable[] = {

691 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,

692 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};

693

695}

696

700 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,

701 Hexagon::P2, Hexagon::P3};

702

704}

705

709 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,

710 Hexagon::Q2, Hexagon::Q3};

711

713}

714

719

720 static const MCPhysReg CtrlRegDecoderTable[] = {

721 SA0, LC0, SA1, LC1,

722 P3_0, C5, M0, M1,

723 USR, PC, UGP, GP,

724 CS0, CS1, UPCYCLELO, UPCYCLEHI,

725 FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,

726 0, 0, 0, 0,

727 0, 0, 0, 0,

728 0, 0, UTIMERLO, UTIMERHI

729 };

730

731 if (RegNo >= std::size(CtrlRegDecoderTable))

733

734 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");

735 if (CtrlRegDecoderTable[RegNo] == NoRegister)

737

738 unsigned Register = CtrlRegDecoderTable[RegNo];

741}

742

747

748 static const MCPhysReg CtrlReg64DecoderTable[] = {

749 C1_0, 0, C3_2, 0,

750 C5_4, 0, C7_6, 0,

751 C9_8, 0, C11_10, 0,

752 CS, 0, UPCYCLE, 0,

753 C17_16, 0, PKTCOUNT, 0,

754 0, 0, 0, 0,

755 0, 0, 0, 0,

756 0, 0, UTIMER, 0

757 };

758

759 if (RegNo >= std::size(CtrlReg64DecoderTable))

761

762 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");

763 if (CtrlReg64DecoderTable[RegNo] == NoRegister)

765

766 unsigned Register = CtrlReg64DecoderTable[RegNo];

769}

770

775 switch (RegNo) {

776 case 0:

778 break;

779 case 1:

781 break;

782 default:

784 }

787}

788

792 HexagonDisassembler const &Disassembler = disassembler(Decoder);

793 int64_t FullValue = fullValue(Disassembler, MI, tmp);

794 assert(FullValue >= 0 && "Negative in unsigned decoder");

797}

798

802 HexagonDisassembler const &Disassembler = disassembler(Decoder);

805 signedDecoder<32>(MI, tmp, Decoder);

807}

808

809

812 HexagonDisassembler const &Disassembler = disassembler(Decoder);

814

815 if (Bits == 0)

816 Bits = 15;

818 uint32_t Extended = FullValue + Address;

819 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0,

820 4))

823}

824

826 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,

827 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,

828 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,

829 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,

830 Hexagon::S12, Hexagon::S13, Hexagon::S14,

831 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,

832 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,

833 Hexagon::VID, Hexagon::S22, Hexagon::S23,

834 Hexagon::S24, Hexagon::S25, Hexagon::S26,

835 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,

836 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,

837 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,

838 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,

839 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,

840 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,

841 Hexagon::S45, Hexagon::S46, Hexagon::S47,

842 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,

843 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,

844 Hexagon::S54, Hexagon::S55, Hexagon::S56,

845 Hexagon::S57, Hexagon::S58, Hexagon::S59,

846 Hexagon::S60, Hexagon::S61, Hexagon::S62,

847 Hexagon::S63, Hexagon::S64, Hexagon::S65,

848 Hexagon::S66, Hexagon::S67, Hexagon::S68,

849 Hexagon::S69, Hexagon::S70, Hexagon::S71,

850 Hexagon::S72, Hexagon::S73, Hexagon::S74,

851 Hexagon::S75, Hexagon::S76, Hexagon::S77,

852 Hexagon::S78, Hexagon::S79, Hexagon::S80,

853};

854

868

870 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,

871 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,

872 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,

873 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,

874 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,

875 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,

876 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,

877 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,

878 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,

879 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,

880};

881

885 RegNo = RegNo >> 1;

888

891

895}

896

901

902 static const MCPhysReg GuestRegDecoderTable[] = {

903 GELR, GSR, GOSP, G3,

904 G4, G5, G6, G7,

905 G8, G9, G10, G11,

906 G12, G13, G14, G15,

907 GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,

908 G20, G21, G22, G23,

909 GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,

910 GPMUCNT2, GPMUCNT3, G30, G31

911 };

912

913 if (RegNo >= std::size(GuestRegDecoderTable))

915 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)

917

918 unsigned Register = GuestRegDecoderTable[RegNo];

921}

922

928

929 static const MCPhysReg GuestReg64DecoderTable[] = {

930 G1_0, 0, G3_2, 0,

931 G5_4, 0, G7_6, 0,

932 G9_8, 0, G11_10, 0,

933 G13_12, 0, G15_14, 0,

934 G17_16, 0, G19_18, 0,

935 G21_20, 0, G23_22, 0,

936 G25_24, 0, G27_26, 0,

937 G29_28, 0, G31_30, 0

938 };

939

940 if (RegNo >= std::size(GuestReg64DecoderTable))

942 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)

944

945 unsigned Register = GuestReg64DecoderTable[RegNo];

948}

MCDisassembler::DecodeStatus DecodeStatus

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define LLVM_EXTERNAL_VISIBILITY

static DecodeStatus sgp10ConstDecoder(MCInst &MI, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:188

static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:597

static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:898

static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:715

static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:810

static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:697

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler()

Definition HexagonDisassembler.cpp:204

static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:799

static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:789

static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:631

static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition HexagonDisassembler.cpp:197

static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:883

static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:771

static const uint16_t SysReg64DecoderTable[]

Definition HexagonDisassembler.cpp:869

static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)

Definition HexagonDisassembler.cpp:586

static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:855

static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:647

static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:182

static const uint16_t SysRegDecoderTable[]

Definition HexagonDisassembler.cpp:825

static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:618

static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:670

static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:602

static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:706

static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:744

static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:660

static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:924

static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition HexagonDisassembler.cpp:687

#define HEXAGON_MAX_PACKET_SIZE

#define HEXAGON_INSTR_SIZE

shuff Hexagon Optimize Shuffle Vector

Promote Memory to Register

static constexpr unsigned IntRegDecoderTable[]

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

ArrayRef< T > slice(size_t N, size_t M) const

slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.

Tagged union holding either a T or a Error.

static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

Superclass for all disassemblers.

MCContext & getContext() const

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

const MCOperand & getOperand(unsigned i) const

Interface to description of machine instruction set.

Instances of this class represent operands of the MCInst class.

static MCOperand createExpr(const MCExpr *Val)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

void setReg(MCRegister Reg)

Set the register number.

MCRegister getReg() const

Returns the register number.

const MCInst * getInst() const

const MCExpr * getExpr() const

static MCOperand createInst(const MCInst *Val)

Generic base class for all target subtargets.

Wrapper class representing virtual and physical registers.

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

void setOuterLoop(MCInst &MCI)

void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)

bool IsReverseVecRegPair(MCRegister VecReg)

size_t bundleSize(MCInst const &MCI)

bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)

unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)

bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn expects newly produced value.

void setInnerLoop(MCInst &MCI)

unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)

unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)

bool IsVecRegPair(MCRegister VecReg)

iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)

bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)

MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)

bool isImmext(MCInst const &MCI)

MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)

bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn produces a second value.

unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)

bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)

MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)

bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)

bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn produces a value.

MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)

Context & getContext() const

friend class Instruction

Iterator for Instructions in a `BasicBlock.

uint32_t read32le(const void *P)

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheHexagonTarget()

unsigned M1(unsigned Val)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

unsigned M0(unsigned Val)

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.