HexagonHazardRecognizer.cpp Source File (original) (raw)

21#include

23using namespace llvm;

25#define DEBUG_TYPE "post-RA-sched"

29 Resources->clearResources();

30 PacketNum = 0;

31 UsesDotCur = nullptr;

32 DotCurPNum = -1;

33 UsesLoad = false;

34 PrefVectorStoreNew = nullptr;

35 RegDefs.clear();

36}

41 if ( || TII->isZeroCost(MI->getOpcode()))

44 if (!Resources->canReserveResources(*MI)) {

45 LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);

47 if (isNewStore(*MI)) {

52 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),

53 MI->getDebugLoc());

54 if (Resources->canReserveResources(*NewMI))

57 << "\n");

58 MF->deleteMachineInstr(NewMI);

59 }

60 return RetVal;

61 }

63 if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) {

64 LLVM_DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", "

65 << *MI);

67 }

70}

74 Resources->clearResources();

75 if (DotCurPNum != -1 && DotCurPNum != (int)PacketNum) {

76 UsesDotCur = nullptr;

77 DotCurPNum = -1;

78 }

79 UsesLoad = false;

80 PrefVectorStoreNew = nullptr;

81 PacketNum++;

82 RegDefs.clear();

83}

96 if (PrefVectorStoreNew != nullptr && PrefVectorStoreNew != SU)

97 return true;

99 return true;

100 return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (int)PacketNum));

101}

102

103

104

105bool HexagonHazardRecognizer::isNewStore(MachineInstr &MI) {

106 if ( TII ->mayBeNewStore(MI))

107 return false;

110}

111

114 if ()

115 return;

116

117

118

122

123 if (TII->isZeroCost(MI->getOpcode()))

124 return;

125

126 if (!Resources->canReserveResources(*MI) || isNewStore(*MI)) {

127

128

129 assert(TII->mayBeNewStore(*MI) && "Expecting .new store");

132 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),

133 MI->getDebugLoc());

134 if (Resources->canReserveResources(*NewMI))

135 Resources->reserveResources(*NewMI);

136 else

137 Resources->reserveResources(*MI);

138 MF->deleteMachineInstr(NewMI);

139 } else

140 Resources->reserveResources(*MI);

142

143

144

145

146

147 if (TII->mayBeCurLoad(*MI))

148 for (auto &S : SU->Succs)

149 if (S.isAssignedRegDep() && S.getLatency() == 0 &&

150 S.getSUnit()->NumPredsLeft == 1) {

151 UsesDotCur = S.getSUnit();

152 DotCurPNum = PacketNum;

153 break;

154 }

155 if (SU == UsesDotCur) {

156 UsesDotCur = nullptr;

157 DotCurPNum = -1;

158 }

159

160 UsesLoad = MI->mayLoad();

161

162 if (TII->isHVXVec(*MI) && ->mayLoad() && ->mayStore())

163 for (auto &S : SU->Succs)

164 if (S.isAssignedRegDep() && S.getLatency() == 0 &&

165 TII->mayBeNewStore(*S.getSUnit()->getInstr()) &&

166 Resources->canReserveResources(*S.getSUnit()->getInstr())) {

167 PrefVectorStoreNew = S.getSUnit();

168 break;

169 }

170}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

void Reset() override

This callback is invoked when a new block of instructions is about to be scheduled.

Definition HexagonHazardRecognizer.cpp:27

void AdvanceCycle() override

This callback is invoked whenever the next top-down instruction to be scheduled cannot issue in the c...

Definition HexagonHazardRecognizer.cpp:72

bool ShouldPreferAnother(SUnit *) override

This callback may be invoked if getHazardType returns NoHazard.

Definition HexagonHazardRecognizer.cpp:95

HazardType getHazardType(SUnit *SU, int stalls) override

Return the hazard type of emitting this node.

Definition HexagonHazardRecognizer.cpp:39

void EmitInstruction(SUnit *) override

This callback is invoked when an instruction is emitted to be scheduled, to advance the hazard state.

Definition HexagonHazardRecognizer.cpp:112

Representation of each machine instruction.

bool mayLoad(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read memory.

LLVM_ABI void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)

Inserts Ops BEFORE It. Can untie/retie tied operands.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

Scheduling unit. This is a node in the scheduling DAG.

bool isInstr() const

Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.

SmallVector< SDep, 4 > Succs

All sunit successors.

MachineInstr * getInstr() const

Returns the representative MachineInstr for this SUnit.

bool contains(const T &V) const

Check if the SmallSet contains the given element.

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.