HexagonMCCompound.cpp Source File (original) (raw)

22#include

23#include

25using namespace llvm;

28#define DEBUG_TYPE "hexagon-mccompound"

42 J4_tstbit0_fp0_jump_nt, J4_tstbit0_fp0_jump_t, J4_tstbit0_fp1_jump_nt,

43 J4_tstbit0_fp1_jump_t, J4_tstbit0_tp0_jump_nt, J4_tstbit0_tp0_jump_t,

44 J4_tstbit0_tp1_jump_nt, J4_tstbit0_tp1_jump_t};

46 J4_cmpeq_fp0_jump_nt, J4_cmpeq_fp0_jump_t, J4_cmpeq_fp1_jump_nt,

47 J4_cmpeq_fp1_jump_t, J4_cmpeq_tp0_jump_nt, J4_cmpeq_tp0_jump_t,

48 J4_cmpeq_tp1_jump_nt, J4_cmpeq_tp1_jump_t};

50 J4_cmpgt_fp0_jump_nt, J4_cmpgt_fp0_jump_t, J4_cmpgt_fp1_jump_nt,

51 J4_cmpgt_fp1_jump_t, J4_cmpgt_tp0_jump_nt, J4_cmpgt_tp0_jump_t,

52 J4_cmpgt_tp1_jump_nt, J4_cmpgt_tp1_jump_t};

54 J4_cmpgtu_fp0_jump_nt, J4_cmpgtu_fp0_jump_t, J4_cmpgtu_fp1_jump_nt,

55 J4_cmpgtu_fp1_jump_t, J4_cmpgtu_tp0_jump_nt, J4_cmpgtu_tp0_jump_t,

56 J4_cmpgtu_tp1_jump_nt, J4_cmpgtu_tp1_jump_t};

58 J4_cmpeqi_fp0_jump_nt, J4_cmpeqi_fp0_jump_t, J4_cmpeqi_fp1_jump_nt,

59 J4_cmpeqi_fp1_jump_t, J4_cmpeqi_tp0_jump_nt, J4_cmpeqi_tp0_jump_t,

60 J4_cmpeqi_tp1_jump_nt, J4_cmpeqi_tp1_jump_t};

62 J4_cmpgti_fp0_jump_nt, J4_cmpgti_fp0_jump_t, J4_cmpgti_fp1_jump_nt,

63 J4_cmpgti_fp1_jump_t, J4_cmpgti_tp0_jump_nt, J4_cmpgti_tp0_jump_t,

64 J4_cmpgti_tp1_jump_nt, J4_cmpgti_tp1_jump_t};

66 J4_cmpgtui_fp0_jump_nt, J4_cmpgtui_fp0_jump_t, J4_cmpgtui_fp1_jump_nt,

67 J4_cmpgtui_fp1_jump_t, J4_cmpgtui_tp0_jump_nt, J4_cmpgtui_tp0_jump_t,

68 J4_cmpgtui_tp1_jump_nt, J4_cmpgtui_tp1_jump_t};

70 J4_cmpeqn1_fp0_jump_nt, J4_cmpeqn1_fp0_jump_t, J4_cmpeqn1_fp1_jump_nt,

71 J4_cmpeqn1_fp1_jump_t, J4_cmpeqn1_tp0_jump_nt, J4_cmpeqn1_tp0_jump_t,

72 J4_cmpeqn1_tp1_jump_nt, J4_cmpeqn1_tp1_jump_t};

74 J4_cmpgtn1_fp0_jump_nt, J4_cmpgtn1_fp0_jump_t, J4_cmpgtn1_fp1_jump_nt,

75 J4_cmpgtn1_fp1_jump_t, J4_cmpgtn1_tp0_jump_nt, J4_cmpgtn1_tp0_jump_t,

76 J4_cmpgtn1_tp1_jump_nt, J4_cmpgtn1_tp1_jump_t,

77};

81 MCRegister DstReg, SrcReg, Src1Reg, Src2Reg;

83 switch (MI.getOpcode()) {

84 default:

92 case Hexagon::C2_cmpeq:

93 case Hexagon::C2_cmpgt:

94 case Hexagon::C2_cmpgtu:

95 if (IsExtended)

97 DstReg = MI.getOperand(0).getReg();

98 Src1Reg = MI.getOperand(1).getReg();

99 Src2Reg = MI.getOperand(2).getReg();

100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&

104 break;

105 case Hexagon::C2_cmpeqi:

106 case Hexagon::C2_cmpgti:

107 case Hexagon::C2_cmpgtui:

108 if (IsExtended)

110

111 DstReg = MI.getOperand(0).getReg();

112 SrcReg = MI.getOperand(1).getReg();

113 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&

118 break;

119 case Hexagon::A2_tfr:

120 if (IsExtended)

122

123 DstReg = MI.getOperand(0).getReg();

124 SrcReg = MI.getOperand(1).getReg();

128 break;

129 case Hexagon::A2_tfrsi:

130 if (IsExtended)

132

133 DstReg = MI.getOperand(0).getReg();

138 break;

139 case Hexagon::S2_tstbit_i:

140 if (IsExtended)

142 DstReg = MI.getOperand(0).getReg();

143 Src1Reg = MI.getOperand(1).getReg();

144 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&

148 break;

149

150

151

152

153 case Hexagon::J2_jumptnew:

154 case Hexagon::J2_jumpfnew:

155 case Hexagon::J2_jumptnewpt:

156 case Hexagon::J2_jumpfnewpt:

157 Src1Reg = MI.getOperand(0).getReg();

158 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)

160 break;

161

162

163

164

165 case Hexagon::J2_jump:

166 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:

168 break;

169 }

170

172}

173

174

178

179 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||

180 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3));

181

183 default:

185 break;

186 case Hexagon::J2_jumpfnew:

188 case Hexagon::J2_jumpfnewpt:

190 case Hexagon::J2_jumptnew:

192 case Hexagon::J2_jumptnewpt:

194 }

195}

196

199 MCInst *CompoundInsn = nullptr;

200 unsigned compoundOpcode;

204

205 switch (L.getOpcode()) {

206 default:

208 return CompoundInsn;

209

210 case Hexagon::A2_tfrsi:

211 Rt = L.getOperand(0);

212 compoundOpcode = J4_jumpseti;

213 CompoundInsn = Context.createMCInst();

214 CompoundInsn->setOpcode(compoundOpcode);

215

217 CompoundInsn->addOperand(L.getOperand(1));

218 CompoundInsn->addOperand(R.getOperand(0));

219 break;

220

221 case Hexagon::A2_tfr:

222 Rt = L.getOperand(0);

223 Rs = L.getOperand(1);

224

225 compoundOpcode = J4_jumpsetr;

226 CompoundInsn = Context.createMCInst();

227 CompoundInsn->setOpcode(compoundOpcode);

230 CompoundInsn->addOperand(R.getOperand(0));

231

232 break;

233

234 case Hexagon::C2_cmpeq:

236 Rs = L.getOperand(1);

237 Rt = L.getOperand(2);

238

240 CompoundInsn = Context.createMCInst();

241 CompoundInsn->setOpcode(compoundOpcode);

244 CompoundInsn->addOperand(R.getOperand(1));

245 break;

246

247 case Hexagon::C2_cmpgt:

249 Rs = L.getOperand(1);

250 Rt = L.getOperand(2);

251

253 CompoundInsn = Context.createMCInst();

254 CompoundInsn->setOpcode(compoundOpcode);

257 CompoundInsn->addOperand(R.getOperand(1));

258 break;

259

260 case Hexagon::C2_cmpgtu:

262 Rs = L.getOperand(1);

263 Rt = L.getOperand(2);

264

266 CompoundInsn = Context.createMCInst();

267 CompoundInsn->setOpcode(compoundOpcode);

270 CompoundInsn->addOperand(R.getOperand(1));

271 break;

272

273 case Hexagon::C2_cmpeqi:

275 Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value);

280 else

282

283 Rs = L.getOperand(1);

284 CompoundInsn = Context.createMCInst();

285 CompoundInsn->setOpcode(compoundOpcode);

287 CompoundInsn->addOperand(L.getOperand(2));

288 CompoundInsn->addOperand(R.getOperand(1));

289 break;

290

291 case Hexagon::C2_cmpgti:

293 Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value);

298 else

300

301 Rs = L.getOperand(1);

302 CompoundInsn = Context.createMCInst();

303 CompoundInsn->setOpcode(compoundOpcode);

305 CompoundInsn->addOperand(L.getOperand(2));

306 CompoundInsn->addOperand(R.getOperand(1));

307 break;

308

309 case Hexagon::C2_cmpgtui:

311 Rs = L.getOperand(1);

313 CompoundInsn = Context.createMCInst();

314 CompoundInsn->setOpcode(compoundOpcode);

316 CompoundInsn->addOperand(L.getOperand(2));

317 CompoundInsn->addOperand(R.getOperand(1));

318 break;

319

320 case Hexagon::S2_tstbit_i:

322 Rs = L.getOperand(1);

324 CompoundInsn = Context.createMCInst();

325 CompoundInsn->setOpcode(compoundOpcode);

327 CompoundInsn->addOperand(R.getOperand(1));

328 break;

329 }

330

331 return CompoundInsn;

332}

333

334

336 MCInst const &MIb, bool IsExtendedB) {

339

340

343 (Opca == Hexagon::A2_tfr || Opca == Hexagon::A2_tfrsi))

344 return true;

347}

348

352 bool JExtended = false;

355 J != MCI.end(); ++J) {

356 MCInst const *JumpInst = J->getInst();

358 JExtended = true;

359 continue;

360 }

362

363 bool BExtended = false;

366 B != MCI.end(); ++B) {

367 MCInst const *Inst = B->getInst();

368 if (JumpInst == Inst) {

369 BExtended = false;

370 continue;

371 }

373 BExtended = true;

374 continue;

375 }

380 if (CompoundInsn) {

382 << JumpInst->getOpcode() << " Compounds to "

383 << CompoundInsn->getOpcode() << "\n");

384 J->setInst(CompoundInsn);

386 return true;

387 }

388 }

389 BExtended = false;

390 }

391 }

392 JExtended = false;

393 }

394 return false;

395}

396

397

398

399

400

404 "Non-Bundle where Bundle expected");

405

406

407 if (MCI.size() < 2)

408 return;

409

410

411 MCInst CheckList(MCI);

412

413

414 MCInst LastValidBundle(MCI);

415

417

418

419

421

422 MCI = CheckList;

423

425 if (PreviouslyValid && !IsValid) {

427 MCI = LastValidBundle;

428 } else if (IsValid) {

429 LastValidBundle = MCI;

430 PreviouslyValid = true;

431 }

432 }

433}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

static bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI)

Definition HexagonMCCompound.cpp:349

static const unsigned cmpgtBitOpcode[8]

Definition HexagonMCCompound.cpp:49

static unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended)

Definition HexagonMCCompound.cpp:80

static const unsigned cmpeqiBitOpcode[8]

Definition HexagonMCCompound.cpp:57

static const unsigned cmpgtuBitOpcode[8]

Definition HexagonMCCompound.cpp:53

static const unsigned cmpeqn1BitOpcode[8]

Definition HexagonMCCompound.cpp:69

static const unsigned cmpgtn1BitOpcode[8]

Definition HexagonMCCompound.cpp:73

static unsigned getCompoundOp(MCInst const &HMCI)

getCompoundOp - Return the index from 0-7 into the above opcode lists.

Definition HexagonMCCompound.cpp:175

static const unsigned cmpgtuiBitOpcode[8]

Definition HexagonMCCompound.cpp:65

static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, MCInst const &MIb, bool IsExtendedB)

Non-Symmetrical. See if these two instructions are fit for compound pair.

Definition HexagonMCCompound.cpp:335

OpcodeIndex

Definition HexagonMCCompound.cpp:30

@ tp1_jump_nt

Definition HexagonMCCompound.cpp:37

@ fp0_jump_nt

Definition HexagonMCCompound.cpp:31

@ fp0_jump_t

Definition HexagonMCCompound.cpp:32

@ tp1_jump_t

Definition HexagonMCCompound.cpp:38

@ fp1_jump_t

Definition HexagonMCCompound.cpp:34

@ fp1_jump_nt

Definition HexagonMCCompound.cpp:33

@ tp0_jump_nt

Definition HexagonMCCompound.cpp:35

@ tp0_jump_t

Definition HexagonMCCompound.cpp:36

static const unsigned cmpeqBitOpcode[8]

Definition HexagonMCCompound.cpp:45

static const unsigned cmpgtiBitOpcode[8]

Definition HexagonMCCompound.cpp:61

static MCInst * getCompoundInsn(MCContext &Context, MCInst const &L, MCInst const &R)

Definition HexagonMCCompound.cpp:197

static const unsigned tstBitOpcode[8]

Definition HexagonMCCompound.cpp:41

Context object for machine code objects.

Instances of this class represent a single low-level machine instruction.

SmallVectorImpl< MCOperand >::iterator iterator

unsigned getOpcode() const

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

Interface to description of machine instruction set.

Instances of this class represent operands of the MCInst class.

MCRegister getReg() const

Returns the register number.

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

bool inRange(MCInst const &MCI, size_t Index)

void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)

tryCompound - Given a bundle check for compound insns when one is found update the contents of the bu...

Definition HexagonMCCompound.cpp:401

bool isBundle(MCInst const &MCI)

int64_t minConstant(MCInst const &MCI, size_t Index)

bool isIntRegForSubInst(MCRegister Reg)

unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)

Return the Hexagon ISA class for the insn.

bool isImmext(MCInst const &MCI)

constexpr size_t bundleInstructionsOffset

This is an optimization pass for GlobalISel generic memory operations.

bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.