HexagonTargetMachine.cpp Source File (original) (raw)

31#include

33using namespace llvm;

37 cl::desc("Enable Hexagon constant-extender optimization"));

40 cl::desc("Enable RDF-based optimizations"));

44 cl::desc("Basic block limit for a function for RDF optimizations"));

48 cl::desc("Disable Hardware Loops for Hexagon target"));

52 cl::desc("Generate widening vector instructions"));

56 cl::desc("Enable optimization of shuffle vectors"));

60 cl::desc("Disable Hexagon Addressing Mode Optimization"));

64 cl::desc("Disable Hexagon CFG Optimization"));

68 cl::desc("Disable Hexagon constant propagation"));

72 cl::desc("Disable Hexagon specific Mask generation pass"));

76 cl::desc("Disable store widening"));

79 cl::desc("Disable load widening"));

83 cl::desc("Early expansion of MUX"));

87 cl::desc("Cleanup of TFRs/COPYs"));

90 cl::desc("Enable early if-conversion"));

94 cl::desc("Enable Hexagon copy hoisting"));

98 cl::desc("Generate \"insert\" instructions"));

102 cl::desc("Enable commoning of GEP instructions"));

103

106 cl::desc("Generate \"extract\" instructions"));

107

110 cl::desc("Enable converting conditional transfers into MUX instructions"));

111

114 cl::desc("Enable conversion of arithmetic operations to "

115 "predicate instructions"));

116

119 cl::desc("Enable loop data prefetch on Hexagon"));

120

123 cl::desc("Disable splitting double registers"));

124

127 cl::desc("Generate absolute set instructions"));

128

131 cl::desc("Bit simplification"));

132

135 cl::desc("Loop rescheduling"));

136

138 cl::desc("Disable backend optimizations"));

139

142 cl::desc("Enable Hexagon Vector print instr pass"));

143

146 cl::desc("Enable vextract optimization"));

147

150 cl::desc("Enable HVX vector combining"));

151

154 cl::desc("Simplify the CFG after atomic expansion pass"));

155

158 cl::desc("Enable instsimplify"));

159

160

161

162

163

164

167

170 C, std::make_unique());

171 DAG->addMutation(std::make_uniqueHexagonSubtarget::UsrOverflowMutation());

172 DAG->addMutation(std::make_uniqueHexagonSubtarget::HVXMemLatencyMutation());

173 DAG->addMutation(std::make_uniqueHexagonSubtarget::CallMutation());

175 return DAG;

176}

177

181

185

233

237 std::optionalReloc::Model RM,

238 std::optionalCodeModel::Model CM,

240

241

242

248 Subtarget(Triple(TT), CPU, FS, *this) {

250}

251

254 AttributeList FnAttrs = F.getAttributes();

255 Attribute CPUAttr = FnAttrs.getFnAttr("target-cpu");

256 Attribute FSAttr = FnAttrs.getFnAttr("target-features");

257

258 std::string CPU =

260 std::string FS =

262

263 auto &I = SubtargetMap[CPU + FS];

264 if () {

265

266

267

269 I = std::make_unique(TargetTriple, CPU, FS, *this);

270 }

271 return I.get();

272}

273

275#define GET_PASS_REGISTRY "HexagonPassRegistry.def"

277

278 PB.registerLateLoopOptimizationsEPCallback(

281 });

282 PB.registerLoopOptimizerEndEPCallback(

285 });

286}

287

292

297 Allocator, F, STI);

298}

299

301

306

307namespace {

308

310public:

313

316 }

317

318 void addIRPasses() override;

319 bool addInstSelector() override;

320 void addPreRegAlloc() override;

321 void addPostRegAlloc() override;

322 void addPreSched2() override;

323 void addPreEmitPass() override;

324};

325}

326

328 return new HexagonPassConfig(*this, PM);

329}

330

331void HexagonPassConfig::addIRPasses() {

333

336

337 if (!NoOpt) {

341 }

342

344

345 if (!NoOpt) {

348 .forwardSwitchCondToPhi(true)

349 .convertSwitchRangeToICmp(true)

350 .convertSwitchToLookupTable(true)

351 .needCanonicalLoops(false)

352 .hoistCommonInsts(true)

353 .sinkCommonInsts(true)));

360

367 }

370 }

371}

372

373bool HexagonPassConfig::addInstSelector() {

376

377 if (!NoOpt)

379

381

382 if (!NoOpt) {

385

388

391

394

398

402 }

408 }

409

410 return false;

411}

412

413void HexagonPassConfig::addPreRegAlloc() {

431 }

434}

435

436void HexagonPassConfig::addPostRegAlloc() {

444 }

445}

446

447void HexagonPassConfig::addPreSched2() {

455}

456

457void HexagonPassConfig::addPreEmitPass() {

459

460 if (!NoOpt)

462

464

465 if (!NoOpt) {

468

471 }

472

473

475

476 if (!NoOpt)

478

481

482

484}

static Reloc::Model getEffectiveRelocModel()

static cl::opt< bool > EnableLoopPrefetch("amdgpu-loop-prefetch", cl::desc("Enable loop data prefetch on AMDGPU"), cl::Hidden, cl::init(false))

#define LLVM_EXTERNAL_VISIBILITY

static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::desc("Early expansion of MUX"))

static cl::opt< bool > EnableCopyHoist("hexagon-copy-hoist", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable Hexagon copy hoisting"))

static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))

static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))

static cl::opt< bool > EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true), cl::desc("Enable HVX vector combining"))

static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))

static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::desc("Disable Hexagon CFG Optimization"))

static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::desc("Disable Hexagon Addressing Mode Optimization"))

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget()

Definition HexagonTargetMachine.cpp:187

static cl::opt< bool > EnableGenWideningVec("hexagon-widening-vectors", cl::init(true), cl::Hidden, cl::desc("Generate widening vector instructions"))

static cl::opt< bool > DisableHCP("disable-hcp", cl::Hidden, cl::desc("Disable Hexagon constant propagation"))

static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))

static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))

static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::desc("Enable Hexagon Vector print instr pass"))

static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)

static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))

static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))

static cl::opt< bool > EnableGenMemAbs("hexagon-mem-abs", cl::init(true), cl::Hidden, cl::desc("Generate absolute set instructions"))

static cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true), cl::desc("Enable vextract optimization"))

static cl::opt< bool > EnableInstSimplify("hexagon-instsimplify", cl::Hidden, cl::init(true), cl::desc("Enable instsimplify"))

static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true), cl::desc("Enable RDF-based optimizations"))

static cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))

static cl::opt< bool > DisableLoadWidening("disable-load-widen", cl::Hidden, cl::desc("Disable load widening"))

int HexagonTargetMachineModule

HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...

Definition HexagonTargetMachine.cpp:165

static cl::opt< bool > DisableHexagonMask("disable-mask", cl::Hidden, cl::desc("Disable Hexagon specific Mask generation pass"))

static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))

static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)

Definition HexagonTargetMachine.cpp:168

static cl::opt< bool > EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(true), cl::Hidden, cl::desc("Cleanup of TFRs/COPYs"))

static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))

static cl::opt< bool > EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass"))

cl::opt< unsigned > RDFFuncBlockLimit("rdf-bb-limit", cl::Hidden, cl::init(1000), cl::desc("Basic block limit for a function for RDF optimizations"))

static cl::opt< bool > EnableOptShuffleVec("hexagon-opt-shuffvec", cl::init(true), cl::Hidden, cl::desc("Enable optimization of shuffle vectors"))

static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden, cl::desc("Enable loop data prefetch on Hexagon"))

static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))

static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::desc("Enable commoning of GEP instructions"))

static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::desc("Enable early if-conversion"))

This file implements a TargetTransformInfo analysis pass specific to the Hexagon target machine.

PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)

const GCNTargetMachine & getTM(const GCNSubtarget *STI)

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

Target-Independent Code Generator Pass Configuration Options pass.

Functions, function parameters, and return types can have attributes to indicate how they should be t...

LLVM_ABI StringRef getValueAsString() const

Return the attribute's value as a string.

bool isValid() const

Return true if the attribute is any kind of attribute.

CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOptLevel OL)

ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...

Definition HexagonTargetMachine.cpp:303

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

Definition HexagonTargetMachine.cpp:293

~HexagonTargetMachine() override

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

Definition HexagonTargetMachine.cpp:327

void registerPassBuilderCallbacks(PassBuilder &PB) override

Allow the target to modify the pass pipeline.

Definition HexagonTargetMachine.cpp:274

HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

Definition HexagonTargetMachine.cpp:234

const HexagonSubtarget * getSubtargetImpl(const Function &F) const override

Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...

Definition HexagonTargetMachine.cpp:253

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

Definition HexagonTargetMachine.cpp:289

MachineSchedRegistry provides a selection of available machine instruction schedulers.

This class provides access to building LLVM's passes.

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

A ScheduleDAG for scheduling lists of MachineInstr.

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...

void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)

Add a postprocessing step to the DAG builder.

const TargetInstrInfo * TII

Target instruction information.

const TargetRegisterInfo * TRI

Target processor register info.

StringRef - Represent a constant reference to a string, i.e.

std::string str() const

str - Get the contents as an std::string.

CodeGenOptLevel getOptLevel() const

Returns the optimization level: None, Less, Default, or Aggressive.

Triple TargetTriple

Triple string, CPU name, and target feature strings the TargetMachine instance is created with.

std::unique_ptr< const MCSubtargetInfo > STI

void resetTargetOptions(const Function &F) const

Reset the target options based on the function's attributes.

Target-Independent Code Generator Pass Configuration Options.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

Interfaces for registering analysis passes, producing common pass manager configurations,...

@ C

The default llvm calling convention, compatible with C.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

FunctionPass * createHexagonVectorPrint()

void initializeHexagonCopyHoistingPass(PassRegistry &)

FunctionPass * createHexagonVectorCombineLegacyPass()

void initializeHexagonOptAddrModePass(PassRegistry &)

LLVM_ABI FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)

void initializeHexagonNewValueJumpPass(PassRegistry &)

char & HexagonTfrCleanupID

FunctionPass * createHexagonCFGOptimizer()

void initializeHexagonSplitConst32AndConst64Pass(PassRegistry &)

void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &)

LLVM_ABI char & RegisterCoalescerID

RegisterCoalescer - This pass merges live ranges to eliminate copies.

void initializeHexagonDAGToDAGISelLegacyPass(PassRegistry &)

void initializeHexagonSplitDoubleRegsPass(PassRegistry &)

FunctionPass * createHexagonOptShuffleVector(const HexagonTargetMachine &)

LLVM_ABI FunctionPass * createDeadCodeEliminationPass()

FunctionPass * createHexagonQFPOptimizer()

void initializeHexagonCommonGEPPass(PassRegistry &)

FunctionPass * createHexagonNewValueJump()

void initializeHexagonRDFOptPass(PassRegistry &)

FunctionPass * createHexagonBranchRelaxation()

FunctionPass * createHexagonLoopAlign()

FunctionPass * createHexagonBitSimplify()

FunctionPass * createHexagonPeephole()

FunctionPass * createHexagonConstExtenders()

FunctionPass * createHexagonConstPropagationPass()

void initializeHexagonGenMemAbsolutePass(PassRegistry &)

FunctionPass * createHexagonFixupHwLoops()

Target & getTheHexagonTarget()

void initializeHexagonMaskPass(PassRegistry &)

void initializeHexagonExpandCondsetsPass(PassRegistry &)

void initializeHexagonAsmPrinterPass(PassRegistry &)

void initializeHexagonVectorPrintPass(PassRegistry &)

FunctionPass * createHexagonMask()

void initializeHexagonPacketizerPass(PassRegistry &)

PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & > LoopPassManager

The Loop pass manager.

FunctionPass * createHexagonPacketizer(bool Minimal)

static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)

CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)

Helper method for getting the code model, returning Default if CM does not have a value.

FunctionPass * createHexagonGenMux()

FunctionPass * createHexagonGenExtract()

LLVM_ABI char & UnreachableMachineBlockElimID

UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.

FunctionPass * createHexagonEarlyIfConversion()

LLVM_ABI FunctionPass * createLoopDataPrefetchPass()

FunctionPass * createHexagonLoadWidening()

void initializeHexagonStoreWideningPass(PassRegistry &)

FunctionPass * createHexagonCallFrameInformation()

FunctionPass * createHexagonHardwareLoops()

void initializeHexagonGenPredicatePass(PassRegistry &)

void initializeHexagonTfrCleanupPass(PassRegistry &)

FunctionPass * createHexagonVExtract()

void initializeHexagonGenMuxPass(PassRegistry &)

void initializeHexagonFixupHwLoopsPass(PassRegistry &)

FunctionPass * createHexagonGenPredicate()

void initializeHexagonVectorCombineLegacyPass(PassRegistry &)

void initializeHexagonCFGOptimizerPass(PassRegistry &)

void initializeHexagonPeepholePass(PassRegistry &)

CodeGenOptLevel

Code generation optimization level.

FunctionPass * createHexagonGenInsert()

void initializeHexagonBranchRelaxationPass(PassRegistry &)

FunctionPass * createHexagonOptimizeSZextends()

FunctionPass * createHexagonLoopRescheduling()

void initializeHexagonCallFrameInformationPass(PassRegistry &)

void initializeHexagonLoopReschedulingPass(PassRegistry &)

void initializeHexagonGenExtractPass(PassRegistry &)

FunctionPass * createHexagonSplitConst32AndConst64()

FunctionPass * createHexagonGenWideningVecFloatInstr(const HexagonTargetMachine &)

FunctionPass * createHexagonCopyToCombine()

LLVM_ABI char & MachinePipelinerID

This pass performs software pipelining on machine instructions.

FunctionPass * createHexagonCommonGEP()

FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOptLevel OptLevel)

createHexagonISelDag - This pass converts a legalized DAG into a Hexagon-specific DAG,...

char & HexagonExpandCondsetsID

void initializeHexagonLoadWideningPass(PassRegistry &)

FunctionPass * createHexagonOptAddrMode()

void initializeHexagonCopyToCombinePass(PassRegistry &)

void initializeHexagonEarlyIfConversionPass(PassRegistry &)

FunctionPass * createHexagonGenMemAbsolute()

void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &)

LLVM_ABI char & VirtRegRewriterID

VirtRegRewriter pass.

FunctionPass * createHexagonSplitDoubleRegs()

void initializeHexagonOptimizeSZextendsPass(PassRegistry &)

void initializeHexagonBitSimplifyPass(PassRegistry &)

LLVM_ABI char & IfConverterID

IfConverter - This pass performs machine code if conversion.

void initializeHexagonConstPropagationPass(PassRegistry &)

LLVM_ABI FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

void initializeHexagonGenInsertPass(PassRegistry &)

BumpPtrAllocatorImpl<> BumpPtrAllocator

The standard BumpPtrAllocator which just uses the default template parameters.

void initializeHexagonConstExtendersPass(PassRegistry &)

FunctionPass * createHexagonStoreWidening()

LLVM_ABI std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)

void initializeHexagonLoopAlignPass(PassRegistry &)

void initializeHexagonHardwareLoopsPass(PassRegistry &)

char & HexagonCopyHoistingID

FunctionPass * createHexagonGenWideningVecInstr(const HexagonTargetMachine &)

void initializeHexagonQFPOptimizerPass(PassRegistry &)

FunctionPass * createHexagonRDFOpt()

LLVM_ABI FunctionPass * createInstSimplifyLegacyPass()

void initializeHexagonVExtractPass(PassRegistry &)

Implement std::hash so that hash_code can be used in STL containers.

Hexagon Vector Loop Carried Reuse Pass.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

static FuncInfoTy * create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)

Factory function: default behavior is to call new using the supplied allocator.

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...

RegisterTargetMachine - Helper template for registering a target machine implementation,...