HexagonTargetMachine.cpp Source File (original) (raw)

30#include

32using namespace llvm;

36 cl::desc("Enable Hexagon constant-extender optimization"));

39 cl::desc("Enable RDF-based optimizations"));

43 cl::desc("Basic block limit for a function for RDF optimizations"));

47 cl::desc("Disable Hardware Loops for Hexagon target"));

51 cl::desc("Disable Hexagon Addressing Mode Optimization"));

55 cl::desc("Disable Hexagon CFG Optimization"));

59 cl::desc("Disable Hexagon constant propagation"));

63 cl::desc("Disable Hexagon specific Mask generation pass"));

67 cl::desc("Disable store widening"));

70 cl::desc("Disable load widening"));

74 cl::desc("Early expansion of MUX"));

78 cl::desc("Cleanup of TFRs/COPYs"));

81 cl::desc("Enable early if-conversion"));

85 cl::desc("Enable Hexagon copy hoisting"));

89 cl::desc("Generate \"insert\" instructions"));

93 cl::desc("Enable commoning of GEP instructions"));

97 cl::desc("Generate \"extract\" instructions"));

101 cl::desc("Enable converting conditional transfers into MUX instructions"));

102

105 cl::desc("Enable conversion of arithmetic operations to "

106 "predicate instructions"));

107

110 cl::desc("Enable loop data prefetch on Hexagon"));

111

114 cl::desc("Disable splitting double registers"));

115

118 cl::desc("Generate absolute set instructions"));

119

122 cl::desc("Bit simplification"));

123

126 cl::desc("Loop rescheduling"));

127

129 cl::desc("Disable backend optimizations"));

130

133 cl::desc("Enable Hexagon Vector print instr pass"));

134

137 cl::desc("Enable vextract optimization"));

138

141 cl::desc("Enable HVX vector combining"));

142

145 cl::desc("Simplify the CFG after atomic expansion pass"));

146

149 cl::desc("Enable instsimplify"));

150

151

152

153

154

155

158

161 C, std::make_unique());

162 DAG->addMutation(std::make_uniqueHexagonSubtarget::UsrOverflowMutation());

163 DAG->addMutation(std::make_uniqueHexagonSubtarget::HVXMemLatencyMutation());

164 DAG->addMutation(std::make_uniqueHexagonSubtarget::CallMutation());

166 return DAG;

167}

168

172

173namespace llvm {

202

240}

241

244}

245

247

249

269}

270

274 std::optionalReloc::Model RM,

275 std::optionalCodeModel::Model CM,

277

278

279

281 T,

282 "e-m:e-p:32:32:32-a:0-n16:32-"

283 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"

284 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",

289 Subtarget(Triple(TT), CPU, FS, *this) {

295}

296

302

303 std::string CPU =

305 std::string FS =

307

308

309

310

311

312 if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())

313 FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;

314

315 auto &I = SubtargetMap[CPU + FS];

316 if () {

317

318

319

321 I = std::make_unique(TargetTriple, CPU, FS, *this);

322 }

323 return I.get();

324}

325

327#define GET_PASS_REGISTRY "HexagonPassRegistry.def"

329

333 });

337 });

338}

339

343}

344

348 return HexagonMachineFunctionInfo::create(

350}

351

353

354namespace {

355

357public:

360

362 return getTM();

363 }

364

368 }

369

370 void addIRPasses() override;

371 bool addInstSelector() override;

372 void addPreRegAlloc() override;

373 void addPostRegAlloc() override;

374 void addPreSched2() override;

375 void addPreEmitPass() override;

376};

377}

378

380 return new HexagonPassConfig(*this, PM);

381}

382

383void HexagonPassConfig::addIRPasses() {

386

387 if (!NoOpt) {

391 }

392

394

395 if (!NoOpt) {

398 .forwardSwitchCondToPhi(true)

399 .convertSwitchRangeToICmp(true)

400 .convertSwitchToLookupTable(true)

401 .needCanonicalLoops(false)

402 .hoistCommonInsts(true)

403 .sinkCommonInsts(true)));

410

413 }

414}

415

416bool HexagonPassConfig::addInstSelector() {

419

420 if (!NoOpt)

422

424

425 if (!NoOpt) {

428

431

434

437

441

445 }

450 }

451

452 return false;

453}

454

455void HexagonPassConfig::addPreRegAlloc() {

473 }

476}

477

478void HexagonPassConfig::addPostRegAlloc() {

486 }

487}

488

489void HexagonPassConfig::addPreSched2() {

497}

498

499void HexagonPassConfig::addPreEmitPass() {

501

502 if (!NoOpt)

504

506

507 if (!NoOpt) {

510

513 }

514

515

517

518 if (!NoOpt)

520

523

524

526}

static cl::opt< bool > EnableLoopPrefetch("amdgpu-loop-prefetch", cl::desc("Enable loop data prefetch on AMDGPU"), cl::Hidden, cl::init(false))

#define LLVM_EXTERNAL_VISIBILITY

static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::desc("Early expansion of MUX"))

static cl::opt< bool > EnableCopyHoist("hexagon-copy-hoist", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable Hexagon copy hoisting"))

static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))

static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))

static cl::opt< bool > EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true), cl::desc("Enable HVX vector combining"))

static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))

static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::desc("Disable Hexagon CFG Optimization"))

static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::desc("Disable Hexagon Addressing Mode Optimization"))

static cl::opt< bool > DisableHCP("disable-hcp", cl::Hidden, cl::desc("Disable Hexagon constant propagation"))

static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))

static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))

static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::desc("Enable Hexagon Vector print instr pass"))

static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)

static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))

static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))

static cl::opt< bool > EnableGenMemAbs("hexagon-mem-abs", cl::init(true), cl::Hidden, cl::desc("Generate absolute set instructions"))

static cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true), cl::desc("Enable vextract optimization"))

static cl::opt< bool > EnableInstSimplify("hexagon-instsimplify", cl::Hidden, cl::init(true), cl::desc("Enable instsimplify"))

static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true), cl::desc("Enable RDF-based optimizations"))

static cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))

static cl::opt< bool > DisableLoadWidening("disable-load-widen", cl::Hidden, cl::desc("Disable load widening"))

static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)

int HexagonTargetMachineModule

HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...

static cl::opt< bool > DisableHexagonMask("disable-mask", cl::Hidden, cl::desc("Disable Hexagon specific Mask generation pass"))

static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))

static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)

static cl::opt< bool > EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(true), cl::Hidden, cl::desc("Cleanup of TFRs/COPYs"))

static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))

static cl::opt< bool > EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass"))

cl::opt< unsigned > RDFFuncBlockLimit("rdf-bb-limit", cl::Hidden, cl::init(1000), cl::desc("Basic block limit for a function for RDF optimizations"))

static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden, cl::desc("Enable loop data prefetch on Hexagon"))

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget()

static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))

static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::desc("Enable commoning of GEP instructions"))

static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::desc("Enable early if-conversion"))

This file implements a TargetTransformInfo analysis pass specific to the Hexagon target machine.

PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)

Target-Independent Code Generator Pass Configuration Options pass.

Attribute getFnAttr(Attribute::AttrKind Kind) const

Return the attribute object that exists for the function.

StringRef getValueAsString() const

Return the attribute's value as a string.

bool isValid() const

Return true if the attribute is any kind of attribute.

Allocate memory in an ever growing pool, as if by bump-pointer.

implements a set of functionality in the TargetMachine class for targets that make use of the indepen...

FunctionPass class - This class is used to implement most global optimizations.

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

~HexagonTargetMachine() override

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

void registerPassBuilderCallbacks(PassBuilder &PB) override

Allow the target to modify the pass pipeline.

HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

const HexagonSubtarget * getSubtargetImpl(const Function &F) const override

Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

MachineSchedRegistry provides a selection of available machine instruction schedulers.

This class provides access to building LLVM's passes.

void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)

void registerLoopOptimizerEndEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)

LLVM_ATTRIBUTE_MINSIZE std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

Pass interface - Implemented by all 'passes'.

A ScheduleDAG for scheduling lists of MachineInstr.

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...

void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)

Add a postprocessing step to the DAG builder.

const TargetInstrInfo * TII

Target instruction information.

const TargetRegisterInfo * TRI

Target processor register info.

StringRef - Represent a constant reference to a string, i.e.

std::string str() const

str - Get the contents as an std::string.

Triple TargetTriple

Triple string, CPU name, and target feature strings the TargetMachine instance is created with.

std::unique_ptr< const MCSubtargetInfo > STI

void resetTargetOptions(const Function &F) const

Reset the target options based on the function's attributes.

Target-Independent Code Generator Pass Configuration Options.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

Interfaces for registering analysis passes, producing common pass manager configurations,...

@ C

The default llvm calling convention, compatible with C.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

FunctionPass * createHexagonVectorPrint()

FunctionPass * createHexagonCopyHoisting()

FunctionPass * createHexagonVectorCombineLegacyPass()

void initializeHexagonOptAddrModePass(PassRegistry &)

FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)

void initializeHexagonNewValueJumpPass(PassRegistry &)

char & HexagonTfrCleanupID

FunctionPass * createHexagonCFGOptimizer()

void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &)

char & RegisterCoalescerID

RegisterCoalescer - This pass merges live ranges to eliminate copies.

void initializeHexagonDAGToDAGISelLegacyPass(PassRegistry &)

void initializeHexagonSplitDoubleRegsPass(PassRegistry &)

FunctionPass * createDeadCodeEliminationPass()

FunctionPass * createHexagonMergeActivateWeight()

Pass * createHexagonLoopIdiomPass()

FunctionPass * createHexagonNewValueJump()

void initializeHexagonRDFOptPass(PassRegistry &)

FunctionPass * createHexagonBranchRelaxation()

FunctionPass * createHexagonLoopAlign()

void initializeHexagonGenMemAbsolutePass(PassRegistry &Registry)

FunctionPass * createHexagonBitSimplify()

FunctionPass * createHexagonPeephole()

FunctionPass * createHexagonConstExtenders()

FunctionPass * createHexagonConstPropagationPass()

FunctionPass * createHexagonFixupHwLoops()

void initializeHexagonCopyHoistingPass(PassRegistry &Registry)

Target & getTheHexagonTarget()

void initializeHexagonMaskPass(PassRegistry &)

void initializeHexagonExpandCondsetsPass(PassRegistry &)

FunctionPass * createHexagonMask()

void initializeHexagonPacketizerPass(PassRegistry &)

FunctionPass * createHexagonPacketizer(bool Minimal)

void initializeHexagonBitSimplifyPass(PassRegistry &Registry)

CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)

Helper method for getting the code model, returning Default if CM does not have a value.

FunctionPass * createHexagonGenMux()

FunctionPass * createHexagonGenExtract()

FunctionPass * createHexagonEarlyIfConversion()

FunctionPass * createLoopDataPrefetchPass()

FunctionPass * createHexagonLoadWidening()

FunctionPass * createHexagonCallFrameInformation()

void initializeHexagonTfrCleanupPass(PassRegistry &)

FunctionPass * createHexagonVExtract()

FunctionPass * createHexagonGenPredicate()

void initializeHexagonVectorCombineLegacyPass(PassRegistry &)

CodeGenOptLevel

Code generation optimization level.

FunctionPass * createHexagonGenInsert()

FunctionPass * createHexagonOptimizeSZextends()

FunctionPass * createHexagonLoopRescheduling()

void initializeHexagonEarlyIfConversionPass(PassRegistry &Registry)

FunctionPass * createHexagonSplitConst32AndConst64()

FunctionPass * createHexagonCopyToCombine()

char & MachinePipelinerID

This pass performs software pipelining on machine instructions.

FunctionPass * createHexagonCommonGEP()

FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOptLevel OptLevel)

createHexagonISelDag - This pass converts a legalized DAG into a Hexagon-specific DAG,...

char & HexagonExpandCondsetsID

FunctionPass * createHexagonOptAddrMode()

void initializeHexagonCopyToCombinePass(PassRegistry &)

FunctionPass * createHexagonGenMemAbsolute()

void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &)

char & VirtRegRewriterID

VirtRegRewriter pass.

FunctionPass * createHexagonTfrCleanup()

FunctionPass * createHexagonSplitDoubleRegs()

FunctionPass * createHexagonHardwareLoops()

void initializeHexagonConstPropagationPass(PassRegistry &Registry)

char & IfConverterID

IfConverter - This pass performs machine code if conversion.

Pass * createHexagonVectorLoopCarriedReuseLegacyPass()

char & UnreachableMachineBlockElimID

UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.

FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

void initializeHexagonConstExtendersPass(PassRegistry &)

FunctionPass * createHexagonStoreWidening()

void initializeHexagonGenMuxPass(PassRegistry &Registry)

std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)

void initializeHexagonLoopAlignPass(PassRegistry &)

void initializeHexagonMergeActivateWeightPass(PassRegistry &)

void initializeHexagonHardwareLoopsPass(PassRegistry &)

char & HexagonCopyHoistingID

FunctionPass * createHexagonRDFOpt()

FunctionPass * createInstSimplifyLegacyPass()

void initializeHexagonVExtractPass(PassRegistry &)

Implement std::hash so that hash_code can be used in STL containers.

Hexagon Vector Loop Carried Reuse Pass.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...

RegisterTargetMachine - Helper template for registering a target machine implementation,...