LLVM: lib/Target/Hexagon/HexagonVLIWPacketizer.h Source File (original) (raw)

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9#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H

10#define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H

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15#include

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17namespace llvm {

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29 std::vector<MachineInstr *> OldPacketMIs;

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32 bool PromotedToDotNew;

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35 bool GlueAllocframeStore;

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38 bool GlueToNewValueJump;

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41 int64_t ChangedOffset;

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45 bool Dependence;

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49 bool FoundSequentialDependence;

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51 bool MemShufDisabled = false;

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54 std::vector<MachineInstr*> IgnoreDepMIs;

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58 bool PacketStalls = false;

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61 unsigned int PacketStallCycles = 0;

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64 bool PacketHasDuplex = false;

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68 bool PacketHasSLOT0OnlyInsn = false;

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70protected:

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75private:

78 const bool Minimal;

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80public:

83 bool Minimal);

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112protected:

114 return MemShufDisabled;

115 };

117 MemShufDisabled = val;

118 };

120 unsigned DepReg);

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138 const MachineInstr &PacketMI, unsigned DepReg);

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151 return PromotedToDotNew;

152 }

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163};

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165}

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167#endif

bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)

bool updateOffset(SUnit *SUI, SUnit *SUJ)

Return true if we can update the offset in MI so that MI and MJ can be packetized together.

void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override

bool getmemShufDisabled()

Definition HexagonVLIWPacketizer.h:113

HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AAResults *AA, const MachineBranchProbabilityInfo *MBPI, bool Minimal)

bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)

bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)

bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)

bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override

bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)

void useCalleesSP(MachineInstr &MI)

bool demoteToDotOld(MachineInstr &MI)

bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)

const MachineLoopInfo * MLI

Definition HexagonVLIWPacketizer.h:73

bool isSoloInstruction(const MachineInstr &MI) override

bool isCurifiable(MachineInstr &MI)

bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override

void initPacketizerState() override

bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)

bool restrictingDepExistInPacket(MachineInstr &, unsigned)

bool producesStall(const MachineInstr &MI)

void undoChangedOffset(MachineInstr &MI)

Undo the changed offset.

bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J)

unsigned int calcStall(const MachineInstr &MI)

bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)

bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)

bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override

void unpacketizeSoloInstrs(MachineFunction &MF)

const MachineBranchProbabilityInfo * MBPI

A handle to the branch probability pass.

Definition HexagonVLIWPacketizer.h:72

bool shouldAddToPacket(const MachineInstr &MI) override

bool canReserveResourcesForConstExt()

bool useCallersSP(MachineInstr &MI)

bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)

bool isPromotedToDotNew() const

Definition HexagonVLIWPacketizer.h:150

bool tryAllocateResourcesForConstExt(bool Reserve)

void setmemShufDisabled(bool val)

Definition HexagonVLIWPacketizer.h:116

void reserveResourcesForConstExt()

MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override

bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)

bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)

bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J)

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

Kind

These are the different kinds of scheduling dependencies.

Scheduling unit. This is a node in the scheduling DAG.

VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AAResults *AA)

This is an optimization pass for GlobalISel generic memory operations.