Host.cpp Source File (original) (raw)

21#include "llvm/Config/llvm-config.h"

30#ifdef LLVM_ON_UNIX

32#include <sched.h>

33#endif

34#ifdef _WIN32

36#endif

37#ifdef _MSC_VER

38#include <intrin.h>

39#endif

40#ifdef __MVS__

42#endif

43#if defined(__APPLE__)

44#include <mach/host_info.h>

45#include <mach/mach.h>

46#include <mach/mach_host.h>

47#include <mach/machine.h>

48#include <sys/param.h>

49#include <sys/sysctl.h>

50#endif

51#ifdef _AIX

52#include <sys/systemcfg.h>

53#endif

54#if defined(__sun__) && defined(__svr4__)

55#include <kstat.h>

56#endif

57#if defined(__GNUC__) || defined(__clang__)

58#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)

59#include <cpuid.h>

60#endif

61#endif

63#define DEBUG_TYPE "host-detection"

71using namespace llvm;

73[[maybe_unused]] static std::unique_ptrllvm::MemoryBuffer

75 const char *CPUInfoFile = "/proc/cpuinfo";

76 if (const char *CpuinfoIntercept = std::getenv("LLVM_CPUINFO"))

77 CPUInfoFile = CpuinfoIntercept;

81 if (std::error_code EC = Text.getError()) {

82 llvm::errs() << "Can't read " << CPUInfoFile << ": " << EC.message()

83 << "\n";

84 return nullptr;

85 }

86 return std::move(*Text);

87}

93 const char *generic = "generic";

101

103 size_t CPULen = 0;

104

105

106

107 while (CIP < CPUInfoEnd && CPUStart == nullptr) {

108 if (CIP < CPUInfoEnd && *CIP == '\n')

109 ++CIP;

110

111 if (CIP < CPUInfoEnd && *CIP == 'c') {

112 ++CIP;

113 if (CIP < CPUInfoEnd && *CIP == 'p') {

114 ++CIP;

115 if (CIP < CPUInfoEnd && *CIP == 'u') {

116 ++CIP;

117 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))

118 ++CIP;

119

120 if (CIP < CPUInfoEnd && *CIP == ':') {

121 ++CIP;

122 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))

123 ++CIP;

124

125 if (CIP < CPUInfoEnd) {

126 CPUStart = CIP;

127 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&

128 *CIP != ',' && *CIP != '\n'))

129 ++CIP;

130 CPULen = CIP - CPUStart;

131 }

132 }

133 }

134 }

135 }

136

137 if (CPUStart == nullptr)

138 while (CIP < CPUInfoEnd && *CIP != '\n')

139 ++CIP;

140 }

141

142 if (CPUStart == nullptr)

143 return generic;

144

146 .Case("604e", "604e")

147 .Case("604", "604")

148 .Case("7400", "7400")

149 .Case("7410", "7400")

150 .Case("7447", "7400")

151 .Case("7455", "7450")

152 .Case("G4", "g4")

153 .Case("POWER4", "970")

154 .Case("PPC970FX", "970")

155 .Case("PPC970MP", "970")

156 .Case("G5", "g5")

157 .Case("POWER5", "g5")

158 .Case("A2", "a2")

159 .Case("POWER6", "pwr6")

160 .Case("POWER7", "pwr7")

161 .Case("POWER8", "pwr8")

162 .Case("POWER8E", "pwr8")

163 .Case("POWER8NVL", "pwr8")

164 .Case("POWER9", "pwr9")

165 .Case("POWER10", "pwr10")

166 .Case("POWER11", "pwr11")

167

168

169

171}

172

177

178 auto MatchBigLittle = [](auto const &Parts, StringRef Big, StringRef Little) {

179 if (Parts.size() == 2)

180 return (Parts[0] == Big && Parts[1] == Little) ||

181 (Parts[1] == Big && Parts[0] == Little);

182 return false;

183 };

184

185 if (Implementer == "0x41") {

186

187

189 return "cortex-a53";

190

191

192 if (MatchBigLittle(Parts, "0xd85", "0xd87"))

193 return "cortex-x925";

194

195

196

197

198

199

201 .Case("0x926", "arm926ej-s")

202 .Case("0xb02", "mpcore")

203 .Case("0xb36", "arm1136j-s")

204 .Case("0xb56", "arm1156t2-s")

205 .Case("0xb76", "arm1176jz-s")

206 .Case("0xc05", "cortex-a5")

207 .Case("0xc07", "cortex-a7")

208 .Case("0xc08", "cortex-a8")

209 .Case("0xc09", "cortex-a9")

210 .Case("0xc0f", "cortex-a15")

211 .Case("0xc0e", "cortex-a17")

212 .Case("0xc20", "cortex-m0")

213 .Case("0xc23", "cortex-m3")

214 .Case("0xc24", "cortex-m4")

215 .Case("0xc27", "cortex-m7")

216 .Case("0xd20", "cortex-m23")

217 .Case("0xd21", "cortex-m33")

218 .Case("0xd24", "cortex-m52")

219 .Case("0xd22", "cortex-m55")

220 .Case("0xd23", "cortex-m85")

221 .Case("0xc18", "cortex-r8")

222 .Case("0xd13", "cortex-r52")

223 .Case("0xd16", "cortex-r52plus")

224 .Case("0xd15", "cortex-r82")

225 .Case("0xd14", "cortex-r82ae")

226 .Case("0xd02", "cortex-a34")

227 .Case("0xd04", "cortex-a35")

228 .Case("0xd8f", "cortex-a320")

229 .Case("0xd03", "cortex-a53")

230 .Case("0xd05", "cortex-a55")

231 .Case("0xd46", "cortex-a510")

232 .Case("0xd80", "cortex-a520")

233 .Case("0xd88", "cortex-a520ae")

234 .Case("0xd07", "cortex-a57")

235 .Case("0xd06", "cortex-a65")

236 .Case("0xd43", "cortex-a65ae")

237 .Case("0xd08", "cortex-a72")

238 .Case("0xd09", "cortex-a73")

239 .Case("0xd0a", "cortex-a75")

240 .Case("0xd0b", "cortex-a76")

241 .Case("0xd0e", "cortex-a76ae")

242 .Case("0xd0d", "cortex-a77")

243 .Case("0xd41", "cortex-a78")

244 .Case("0xd42", "cortex-a78ae")

245 .Case("0xd4b", "cortex-a78c")

246 .Case("0xd47", "cortex-a710")

247 .Case("0xd4d", "cortex-a715")

248 .Case("0xd81", "cortex-a720")

249 .Case("0xd89", "cortex-a720ae")

250 .Case("0xd87", "cortex-a725")

251 .Case("0xd44", "cortex-x1")

252 .Case("0xd4c", "cortex-x1c")

253 .Case("0xd48", "cortex-x2")

254 .Case("0xd4e", "cortex-x3")

255 .Case("0xd82", "cortex-x4")

256 .Case("0xd85", "cortex-x925")

257 .Case("0xd4a", "neoverse-e1")

258 .Case("0xd0c", "neoverse-n1")

259 .Case("0xd49", "neoverse-n2")

260 .Case("0xd8e", "neoverse-n3")

261 .Case("0xd40", "neoverse-v1")

262 .Case("0xd4f", "neoverse-v2")

263 .Case("0xd84", "neoverse-v3")

264 .Case("0xd83", "neoverse-v3ae")

266 }

267

268 if (Implementer == "0x42" || Implementer == "0x43") {

270 .Case("0x516", "thunderx2t99")

271 .Case("0x0516", "thunderx2t99")

272 .Case("0xaf", "thunderx2t99")

273 .Case("0x0af", "thunderx2t99")

274 .Case("0xa1", "thunderxt88")

275 .Case("0x0a1", "thunderxt88")

277 }

278

279 if (Implementer == "0x46") {

281 .Case("0x001", "a64fx")

282 .Case("0x003", "fujitsu-monaka")

284 }

285

286 if (Implementer == "0x4e") {

288 .Case("0x004", "carmel")

289 .Case("0x10", "olympus")

290 .Case("0x010", "olympus")

292 }

293

294 if (Implementer == "0x48")

295

296

297

299 .Case("0xd01", "tsv110")

301

302 if (Implementer == "0x51")

303

304

305

307 .Case("0x06f", "krait")

308 .Case("0x201", "kryo")

309 .Case("0x205", "kryo")

310 .Case("0x211", "kryo")

311 .Case("0x800", "cortex-a73")

312 .Case("0x801", "cortex-a73")

313 .Case("0x802", "cortex-a75")

314 .Case("0x803", "cortex-a75")

315 .Case("0x804", "cortex-a76")

316 .Case("0x805", "cortex-a76")

317 .Case("0xc00", "falkor")

318 .Case("0xc01", "saphira")

319 .Case("0x001", "oryon-1")

321 if (Implementer == "0x53") {

322

323

324

325

326

327 unsigned Variant = GetVariant();

328

329

330

331 unsigned PartAsInt;

333

334 unsigned Exynos = (Variant << 12) | PartAsInt;

335 switch (Exynos) {

336 default:

337

338 [[fallthrough]];

339 case 0x1002:

340 return "exynos-m3";

341 case 0x1003:

342 return "exynos-m4";

343 }

344 }

345

346 if (Implementer == "0x61") {

348 .Case("0x020", "apple-m1")

349 .Case("0x021", "apple-m1")

350 .Case("0x022", "apple-m1")

351 .Case("0x023", "apple-m1")

352 .Case("0x024", "apple-m1")

353 .Case("0x025", "apple-m1")

354 .Case("0x028", "apple-m1")

355 .Case("0x029", "apple-m1")

356 .Case("0x030", "apple-m2")

357 .Case("0x031", "apple-m2")

358 .Case("0x032", "apple-m2")

359 .Case("0x033", "apple-m2")

360 .Case("0x034", "apple-m2")

361 .Case("0x035", "apple-m2")

362 .Case("0x038", "apple-m2")

363 .Case("0x039", "apple-m2")

364 .Case("0x049", "apple-m3")

365 .Case("0x048", "apple-m3")

367 }

368

369 if (Implementer == "0x63") {

371 .Case("0x132", "star-mc1")

372 .Case("0xd25", "star-mc3")

374 }

375

376 if (Implementer == "0x6d") {

377

379 .Case("0xd49", "neoverse-n2")

381 }

382

383 if (Implementer == "0xc0") {

385 .Case("0xac3", "ampere1")

386 .Case("0xac4", "ampere1a")

387 .Case("0xac5", "ampere1b")

389 }

390

391 return "generic";

392}

393

395

396

397

398

399

401 ProcCpuinfoContent.split(Lines, '\n');

402

403

404

409 if (Line.consume_front("CPU implementer"))

410 Implementer = Line.ltrim("\t :");

411 else if (Line.consume_front("Hardware"))

412 Hardware = Line.ltrim("\t :");

413 else if (Line.consume_front("CPU part"))

415 }

416

417

419

420

423

424 auto GetVariant = [&]() {

425 unsigned Variant = 0;

426 for (auto I : Lines)

427 if (I.consume_front("CPU variant"))

428 I.ltrim("\t :").getAsInteger(0, Variant);

429 return Variant;

430 };

431

433 GetVariant);

434}

435

438

442

444 PartsHolder.reserve(UniqueCpuInfos.size());

445 for (auto Info : UniqueCpuInfos)

447 true,

448 3));

449

452 for (const auto &Part : PartsHolder)

454

457 true,

458 2),

459 "",

461 true,

462 3),

464}

465

466namespace {

467StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {

468 switch (Id) {

469 case 2064:

470 case 2066:

471 case 2084:

472 case 2086:

473 case 2094:

474 case 2096:

475 return "generic";

476 case 2097:

477 case 2098:

478 return "z10";

479 case 2817:

480 case 2818:

481 return "z196";

482 case 2827:

483 case 2828:

484 return "zEC12";

485 case 2964:

486 case 2965:

487 return HaveVectorSupport? "z13" : "zEC12";

488 case 3906:

489 case 3907:

490 return HaveVectorSupport? "z14" : "zEC12";

491 case 8561:

492 case 8562:

493 return HaveVectorSupport? "z15" : "zEC12";

494 case 3931:

495 case 3932:

496 return HaveVectorSupport? "z16" : "zEC12";

497 case 9175:

498 case 9176:

499 default:

500 return HaveVectorSupport? "z17" : "zEC12";

501 }

502}

503}

504

506

507

508

509

511 ProcCpuinfoContent.split(Lines, '\n');

512

513

516 if (Line.starts_with("features")) {

517 size_t Pos = Line.find(':');

519 Line.drop_front(Pos + 1).split(CPUFeatures, ' ');

520 break;

521 }

522 }

523

524

525

526

528

529

531 if (Line.starts_with("processor ")) {

532 size_t Pos = Line.find("machine = ");

534 Pos += sizeof("machine = ") - 1;

535 unsigned int Id;

536 if (!Line.drop_front(Pos).getAsInteger(10, Id))

537 return getCPUNameFromS390Model(Id, HaveVectorSupport);

538 }

539 break;

540 }

541 }

542

543 return "generic";

544}

545

547

549 ProcCpuinfoContent.split(Lines, '\n');

550

551

554 if (Line.starts_with("uarch")) {

556 break;

557 }

558 }

559

561 .Case("eswin,eic770x", "sifive-p550")

562 .Case("sifive,u74-mc", "sifive-u74")

563 .Case("sifive,bullet0", "sifive-u74")

565}

566

568#if !defined(__linux__) || !defined(__x86_64__)

569 return "generic";

570#else

571 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =

572

573 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

574

575 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,

576

577 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,

578

579 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,

580

581 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };

582

583 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =

584

585 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

586

587 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,

588

589 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,

590

591 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,

592

593 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };

594

595 struct bpf_prog_load_attr {

605 } attr = {};

606 attr.prog_type = 1;

607 attr.insn_cnt = 5;

608 attr.insns = (uint64_t)v3_insns;

609 attr.license = (uint64_t)"DUMMY";

610

611 int fd = syscall(321 , 5 , &attr,

612 sizeof(attr));

613 if (fd >= 0) {

614 close(fd);

615 return "v3";

616 }

617

618

619 memset(&attr, 0, sizeof(attr));

620 attr.prog_type = 1;

621 attr.insn_cnt = 5;

622 attr.insns = (uint64_t)v2_insns;

623 attr.license = (uint64_t)"DUMMY";

624 fd = syscall(321 , 5 , &attr, sizeof(attr));

625 if (fd >= 0) {

626 close(fd);

627 return "v2";

628 }

629 return "v1";

630#endif

631}

632

633#if (defined(__i386__) || defined(_M_IX86) || defined(__x86_64__) || \

634 defined(_M_X64)) && \

635 !defined(_M_ARM64EC)

636

637

638

639static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,

640 unsigned *rECX, unsigned *rEDX) {

641#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)

642 return !__get_cpuid(value, rEAX, rEBX, rECX, rEDX);

643#elif defined(_MSC_VER)

644

645 int registers[4];

646 __cpuid(registers, value);

647 *rEAX = registers[0];

648 *rEBX = registers[1];

649 *rECX = registers[2];

650 *rEDX = registers[3];

651 return false;

652#else

653 return true;

654#endif

655}

656

657namespace llvm {

658namespace sys {

660namespace x86 {

661

662VendorSignatures getVendorSignature(unsigned *MaxLeaf) {

663 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;

664 if (MaxLeaf == nullptr)

665 MaxLeaf = &EAX;

666 else

667 *MaxLeaf = 0;

668

669 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)

670 return VendorSignatures::UNKNOWN;

671

672

673 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)

674 return VendorSignatures::GENUINE_INTEL;

675

676

677 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)

678 return VendorSignatures::AUTHENTIC_AMD;

679

680 return VendorSignatures::UNKNOWN;

681}

682

683}

684}

685}

686}

687

689

690

691

692

693static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,

694 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,

695 unsigned *rEDX) {

696

697

698

699

700#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)

701 return !__get_cpuid_count(value, subleaf, rEAX, rEBX, rECX, rEDX);

702#elif defined(_MSC_VER)

703 int registers[4];

704 __cpuidex(registers, value, subleaf);

705 *rEAX = registers[0];

706 *rEBX = registers[1];

707 *rECX = registers[2];

708 *rEDX = registers[3];

709 return false;

710#else

711 return true;

712#endif

713}

714

715

716static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {

717

718

719

720#if defined(__GNUC__) || defined(__clang__)

721

722

723

724 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));

725 return false;

726#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)

727 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);

729 *rEDX = Result >> 32;

730 return false;

731#else

732 return true;

733#endif

734}

735

736static void detectX86FamilyModel(unsigned EAX, unsigned *Family,

737 unsigned *Model) {

738 *Family = (EAX >> 8) & 0xf;

739 *Model = (EAX >> 4) & 0xf;

740 if (*Family == 6 || *Family == 0xf) {

741 if (*Family == 0xf)

742

743 *Family += (EAX >> 20) & 0xff;

744

745 *Model += ((EAX >> 16) & 0xf) << 4;

746 }

747}

748

749#define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0

750

751static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,

752 unsigned Model,

753 const unsigned *Features,

754 unsigned *Type,

755 unsigned *Subtype) {

757

758 switch (Family) {

759 case 0x3:

760 CPU = "i386";

761 break;

762 case 0x4:

763 CPU = "i486";

764 break;

765 case 0x5:

766 if (testFeature(X86::FEATURE_MMX)) {

767 CPU = "pentium-mmx";

768 break;

769 }

770 CPU = "pentium";

771 break;

772 case 0x6:

773 switch (Model) {

774 case 0x0f:

775

776

777

778

779 case 0x16:

780

781 CPU = "core2";

782 *Type = X86::INTEL_CORE2;

783 break;

784 case 0x17:

785

786

787

788 case 0x1d:

789

790 CPU = "penryn";

791 *Type = X86::INTEL_CORE2;

792 break;

793 case 0x1a:

794

795 case 0x1e:

796

797 case 0x1f:

798 case 0x2e:

799 CPU = "nehalem";

800 *Type = X86::INTEL_COREI7;

801 *Subtype = X86::INTEL_COREI7_NEHALEM;

802 break;

803 case 0x25:

804 case 0x2c:

805

806 case 0x2f:

807 CPU = "westmere";

808 *Type = X86::INTEL_COREI7;

809 *Subtype = X86::INTEL_COREI7_WESTMERE;

810 break;

811 case 0x2a:

812

813 case 0x2d:

814 CPU = "sandybridge";

815 *Type = X86::INTEL_COREI7;

816 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;

817 break;

818 case 0x3a:

819 case 0x3e:

820 CPU = "ivybridge";

821 *Type = X86::INTEL_COREI7;

822 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;

823 break;

824

825

826 case 0x3c:

827 case 0x3f:

828 case 0x45:

829 case 0x46:

830 CPU = "haswell";

831 *Type = X86::INTEL_COREI7;

832 *Subtype = X86::INTEL_COREI7_HASWELL;

833 break;

834

835

836 case 0x3d:

837 case 0x47:

838 case 0x4f:

839 case 0x56:

840 CPU = "broadwell";

841 *Type = X86::INTEL_COREI7;

842 *Subtype = X86::INTEL_COREI7_BROADWELL;

843 break;

844

845

846 case 0x4e:

847 case 0x5e:

848 case 0x8e:

849 case 0x9e:

850 case 0xa5:

851 case 0xa6:

852 CPU = "skylake";

853 *Type = X86::INTEL_COREI7;

854 *Subtype = X86::INTEL_COREI7_SKYLAKE;

855 break;

856

857

858 case 0xa7:

859 CPU = "rocketlake";

860 *Type = X86::INTEL_COREI7;

861 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;

862 break;

863

864

865 case 0x55:

866 *Type = X86::INTEL_COREI7;

867 if (testFeature(X86::FEATURE_AVX512BF16)) {

868 CPU = "cooperlake";

869 *Subtype = X86::INTEL_COREI7_COOPERLAKE;

870 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {

871 CPU = "cascadelake";

872 *Subtype = X86::INTEL_COREI7_CASCADELAKE;

873 } else {

874 CPU = "skylake-avx512";

875 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;

876 }

877 break;

878

879

880 case 0x66:

881 CPU = "cannonlake";

882 *Type = X86::INTEL_COREI7;

883 *Subtype = X86::INTEL_COREI7_CANNONLAKE;

884 break;

885

886

887 case 0x7d:

888 case 0x7e:

889 CPU = "icelake-client";

890 *Type = X86::INTEL_COREI7;

891 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;

892 break;

893

894

895 case 0x8c:

896 case 0x8d:

897 CPU = "tigerlake";

898 *Type = X86::INTEL_COREI7;

899 *Subtype = X86::INTEL_COREI7_TIGERLAKE;

900 break;

901

902

903 case 0x97:

904 case 0x9a:

905 CPU = "alderlake";

906 *Type = X86::INTEL_COREI7;

907 *Subtype = X86::INTEL_COREI7_ALDERLAKE;

908 break;

909

910

911 case 0xbe:

912 CPU = "gracemont";

913 *Type = X86::INTEL_COREI7;

914 *Subtype = X86::INTEL_COREI7_ALDERLAKE;

915 break;

916

917

918 case 0xb7:

919 case 0xba:

920 case 0xbf:

921 CPU = "raptorlake";

922 *Type = X86::INTEL_COREI7;

923 *Subtype = X86::INTEL_COREI7_ALDERLAKE;

924 break;

925

926

927 case 0xaa:

928 case 0xac:

929 CPU = "meteorlake";

930 *Type = X86::INTEL_COREI7;

931 *Subtype = X86::INTEL_COREI7_ALDERLAKE;

932 break;

933

934

935 case 0xc5:

936

937 case 0xb5:

938 CPU = "arrowlake";

939 *Type = X86::INTEL_COREI7;

940 *Subtype = X86::INTEL_COREI7_ARROWLAKE;

941 break;

942

943

944 case 0xc6:

945 CPU = "arrowlake-s";

946 *Type = X86::INTEL_COREI7;

947 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;

948 break;

949

950

951 case 0xbd:

952 CPU = "lunarlake";

953 *Type = X86::INTEL_COREI7;

954 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;

955 break;

956

957

958 case 0xcc:

959 CPU = "pantherlake";

960 *Type = X86::INTEL_COREI7;

961 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;

962 break;

963

964

965 case 0xd5:

966 CPU = "wildcatlake";

967 *Type = X86::INTEL_COREI7;

968 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;

969 break;

970

971

972 case 0xad:

973 CPU = "graniterapids";

974 *Type = X86::INTEL_COREI7;

975 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;

976 break;

977

978

979 case 0xae:

980 CPU = "graniterapids-d";

981 *Type = X86::INTEL_COREI7;

982 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;

983 break;

984

985

986 case 0x6a:

987 case 0x6c:

988 CPU = "icelake-server";

989 *Type = X86::INTEL_COREI7;

990 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;

991 break;

992

993

994 case 0xcf:

995 CPU = "emeraldrapids";

996 *Type = X86::INTEL_COREI7;

997 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;

998 break;

999

1000

1001 case 0x8f:

1002 CPU = "sapphirerapids";

1003 *Type = X86::INTEL_COREI7;

1004 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;

1005 break;

1006

1007 case 0x1c:

1008 case 0x26:

1009 case 0x27:

1010 case 0x35:

1011 case 0x36:

1012 CPU = "bonnell";

1013 *Type = X86::INTEL_BONNELL;

1014 break;

1015

1016

1017 case 0x37:

1018 case 0x4a:

1019 case 0x4d:

1020 case 0x5a:

1021 case 0x5d:

1022 case 0x4c:

1023 CPU = "silvermont";

1024 *Type = X86::INTEL_SILVERMONT;

1025 break;

1026

1027 case 0x5c:

1028 case 0x5f:

1029 CPU = "goldmont";

1030 *Type = X86::INTEL_GOLDMONT;

1031 break;

1032 case 0x7a:

1033 CPU = "goldmont-plus";

1034 *Type = X86::INTEL_GOLDMONT_PLUS;

1035 break;

1036 case 0x86:

1037 case 0x8a:

1038 case 0x96:

1039 case 0x9c:

1040 CPU = "tremont";

1041 *Type = X86::INTEL_TREMONT;

1042 break;

1043

1044

1045 case 0xaf:

1046 CPU = "sierraforest";

1047 *Type = X86::INTEL_SIERRAFOREST;

1048 break;

1049

1050

1051 case 0xb6:

1052 CPU = "grandridge";

1053 *Type = X86::INTEL_GRANDRIDGE;

1054 break;

1055

1056

1057 case 0xdd:

1058 CPU = "clearwaterforest";

1059 *Type = X86::INTEL_CLEARWATERFOREST;

1060 break;

1061

1062

1063 case 0x57:

1064 CPU = "knl";

1065 *Type = X86::INTEL_KNL;

1066 break;

1067 case 0x85:

1068 CPU = "knm";

1069 *Type = X86::INTEL_KNM;

1070 break;

1071

1072 default:

1073

1074

1075

1076 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {

1077 CPU = "tigerlake";

1078 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {

1079 CPU = "icelake-client";

1080 } else if (testFeature(X86::FEATURE_AVX512VBMI)) {

1081 CPU = "cannonlake";

1082 } else if (testFeature(X86::FEATURE_AVX512BF16)) {

1083 CPU = "cooperlake";

1084 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {

1085 CPU = "cascadelake";

1086 } else if (testFeature(X86::FEATURE_AVX512VL)) {

1087 CPU = "skylake-avx512";

1088 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {

1089 if (testFeature(X86::FEATURE_SHA))

1090 CPU = "goldmont";

1091 else

1092 CPU = "skylake";

1093 } else if (testFeature(X86::FEATURE_ADX)) {

1094 CPU = "broadwell";

1095 } else if (testFeature(X86::FEATURE_AVX2)) {

1096 CPU = "haswell";

1097 } else if (testFeature(X86::FEATURE_AVX)) {

1098 CPU = "sandybridge";

1099 } else if (testFeature(X86::FEATURE_SSE4_2)) {

1100 if (testFeature(X86::FEATURE_MOVBE))

1101 CPU = "silvermont";

1102 else

1103 CPU = "nehalem";

1104 } else if (testFeature(X86::FEATURE_SSE4_1)) {

1105 CPU = "penryn";

1106 } else if (testFeature(X86::FEATURE_SSSE3)) {

1107 if (testFeature(X86::FEATURE_MOVBE))

1108 CPU = "bonnell";

1109 else

1110 CPU = "core2";

1111 } else if (testFeature(X86::FEATURE_64BIT)) {

1112 CPU = "core2";

1113 } else if (testFeature(X86::FEATURE_SSE3)) {

1114 CPU = "yonah";

1115 } else if (testFeature(X86::FEATURE_SSE2)) {

1116 CPU = "pentium-m";

1117 } else if (testFeature(X86::FEATURE_SSE)) {

1118 CPU = "pentium3";

1119 } else if (testFeature(X86::FEATURE_MMX)) {

1120 CPU = "pentium2";

1121 } else {

1122 CPU = "pentiumpro";

1123 }

1124 break;

1125 }

1126 break;

1127 case 0xf: {

1128 if (testFeature(X86::FEATURE_64BIT)) {

1129 CPU = "nocona";

1130 break;

1131 }

1132 if (testFeature(X86::FEATURE_SSE3)) {

1133 CPU = "prescott";

1134 break;

1135 }

1136 CPU = "pentium4";

1137 break;

1138 }

1139 case 0x13:

1140 switch (Model) {

1141

1142 case 0x01:

1143 CPU = "diamondrapids";

1144 *Type = X86::INTEL_COREI7;

1145 *Subtype = X86::INTEL_COREI7_DIAMONDRAPIDS;

1146 break;

1147

1148 default:

1149 break;

1150 }

1151 break;

1152 case 0x12:

1153 switch (Model) {

1154

1155 case 0x1:

1156 case 0x3:

1157 CPU = "novalake";

1158 *Type = X86::INTEL_COREI7;

1159 *Subtype = X86::INTEL_COREI7_NOVALAKE;

1160 break;

1161 default:

1162 break;

1163 }

1164 break;

1165

1166 default:

1167 break;

1168 }

1169

1170 return CPU;

1171}

1172

1173static const char *getAMDProcessorTypeAndSubtype(unsigned Family,

1174 unsigned Model,

1175 const unsigned *Features,

1176 unsigned *Type,

1177 unsigned *Subtype) {

1178 const char *CPU = nullptr;

1179

1180 switch (Family) {

1181 case 4:

1182 CPU = "i486";

1183 break;

1184 case 5:

1185 CPU = "pentium";

1186 switch (Model) {

1187 case 6:

1188 case 7:

1189 CPU = "k6";

1190 break;

1191 case 8:

1192 CPU = "k6-2";

1193 break;

1194 case 9:

1195 case 13:

1196 CPU = "k6-3";

1197 break;

1198 case 10:

1199 CPU = "geode";

1200 break;

1201 }

1202 break;

1203 case 6:

1204 if (testFeature(X86::FEATURE_SSE)) {

1205 CPU = "athlon-xp";

1206 break;

1207 }

1208 CPU = "athlon";

1209 break;

1210 case 15:

1211 if (testFeature(X86::FEATURE_SSE3)) {

1212 CPU = "k8-sse3";

1213 break;

1214 }

1215 CPU = "k8";

1216 break;

1217 case 16:

1218 case 18:

1219 CPU = "amdfam10";

1220 *Type = X86::AMDFAM10H;

1221 switch (Model) {

1222 case 2:

1223 *Subtype = X86::AMDFAM10H_BARCELONA;

1224 break;

1225 case 4:

1226 *Subtype = X86::AMDFAM10H_SHANGHAI;

1227 break;

1228 case 8:

1229 *Subtype = X86::AMDFAM10H_ISTANBUL;

1230 break;

1231 }

1232 break;

1233 case 20:

1234 CPU = "btver1";

1235 *Type = X86::AMD_BTVER1;

1236 break;

1237 case 21:

1238 CPU = "bdver1";

1239 *Type = X86::AMDFAM15H;

1240 if (Model >= 0x60 && Model <= 0x7f) {

1241 CPU = "bdver4";

1242 *Subtype = X86::AMDFAM15H_BDVER4;

1243 break;

1244 }

1245 if (Model >= 0x30 && Model <= 0x3f) {

1246 CPU = "bdver3";

1247 *Subtype = X86::AMDFAM15H_BDVER3;

1248 break;

1249 }

1250 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {

1251 CPU = "bdver2";

1252 *Subtype = X86::AMDFAM15H_BDVER2;

1253 break;

1254 }

1255 if (Model <= 0x0f) {

1256 *Subtype = X86::AMDFAM15H_BDVER1;

1257 break;

1258 }

1259 break;

1260 case 22:

1261 CPU = "btver2";

1262 *Type = X86::AMD_BTVER2;

1263 break;

1264 case 23:

1265 CPU = "znver1";

1266 *Type = X86::AMDFAM17H;

1267 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) ||

1268 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) ||

1269 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) ||

1270 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) ||

1271 (Model >= 0xa0 && Model <= 0xaf)) {

1272

1273

1274

1275

1276

1277

1278

1279

1280

1281 CPU = "znver2";

1282 *Subtype = X86::AMDFAM17H_ZNVER2;

1283 break;

1284 }

1285 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) {

1286

1287

1288

1289 *Subtype = X86::AMDFAM17H_ZNVER1;

1290 break;

1291 }

1292 break;

1293 case 25:

1294 CPU = "znver3";

1295 *Type = X86::AMDFAM19H;

1296 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||

1297 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||

1298 (Model >= 0x50 && Model <= 0x5f)) {

1299

1300

1301

1302

1303

1304 *Subtype = X86::AMDFAM19H_ZNVER3;

1305 break;

1306 }

1307 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) ||

1308 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) ||

1309 (Model >= 0xa0 && Model <= 0xaf)) {

1310

1311

1312

1313

1314

1315 CPU = "znver4";

1316 *Subtype = X86::AMDFAM19H_ZNVER4;

1317 break;

1318 }

1319 break;

1320 case 26:

1321 CPU = "znver5";

1322 *Type = X86::AMDFAM1AH;

1323 if (Model <= 0x4f || (Model >= 0x60 && Model <= 0x77) ||

1324 (Model >= 0xd0 && Model <= 0xd7)) {

1325

1326

1327

1328

1329

1330

1331

1332

1333

1334 CPU = "znver5";

1335 *Subtype = X86::AMDFAM1AH_ZNVER5;

1336 break;

1337 }

1338 break;

1339

1340 default:

1341 break;

1342 }

1343

1344 return CPU;

1345}

1346

1347#undef testFeature

1348

1349static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,

1350 unsigned *Features) {

1352

1353 auto setFeature = [&](unsigned F) {

1354 Features[F / 32] |= 1U << (F % 32);

1355 };

1356

1357 if ((EDX >> 15) & 1)

1358 setFeature(X86::FEATURE_CMOV);

1359 if ((EDX >> 23) & 1)

1360 setFeature(X86::FEATURE_MMX);

1361 if ((EDX >> 25) & 1)

1362 setFeature(X86::FEATURE_SSE);

1363 if ((EDX >> 26) & 1)

1364 setFeature(X86::FEATURE_SSE2);

1365

1366 if ((ECX >> 0) & 1)

1367 setFeature(X86::FEATURE_SSE3);

1368 if ((ECX >> 1) & 1)

1369 setFeature(X86::FEATURE_PCLMUL);

1370 if ((ECX >> 9) & 1)

1371 setFeature(X86::FEATURE_SSSE3);

1372 if ((ECX >> 12) & 1)

1373 setFeature(X86::FEATURE_FMA);

1374 if ((ECX >> 19) & 1)

1375 setFeature(X86::FEATURE_SSE4_1);

1376 if ((ECX >> 20) & 1) {

1377 setFeature(X86::FEATURE_SSE4_2);

1378 setFeature(X86::FEATURE_CRC32);

1379 }

1380 if ((ECX >> 23) & 1)

1381 setFeature(X86::FEATURE_POPCNT);

1382 if ((ECX >> 25) & 1)

1383 setFeature(X86::FEATURE_AES);

1384

1385 if ((ECX >> 22) & 1)

1386 setFeature(X86::FEATURE_MOVBE);

1387

1388

1389

1390

1391 const unsigned AVXBits = (1 << 27) | (1 << 28);

1392 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&

1393 ((EAX & 0x6) == 0x6);

1394#if defined(__APPLE__)

1395

1396

1397

1398 bool HasAVX512Save = true;

1399#else

1400

1401 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);

1402#endif

1403

1404 if (HasAVX)

1405 setFeature(X86::FEATURE_AVX);

1406

1407 bool HasLeaf7 =

1408 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);

1409

1410 if (HasLeaf7 && ((EBX >> 3) & 1))

1411 setFeature(X86::FEATURE_BMI);

1412 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)

1413 setFeature(X86::FEATURE_AVX2);

1414 if (HasLeaf7 && ((EBX >> 8) & 1))

1415 setFeature(X86::FEATURE_BMI2);

1416 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) {

1417 setFeature(X86::FEATURE_AVX512F);

1418 }

1419 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)

1420 setFeature(X86::FEATURE_AVX512DQ);

1421 if (HasLeaf7 && ((EBX >> 19) & 1))

1422 setFeature(X86::FEATURE_ADX);

1423 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)

1424 setFeature(X86::FEATURE_AVX512IFMA);

1425 if (HasLeaf7 && ((EBX >> 23) & 1))

1426 setFeature(X86::FEATURE_CLFLUSHOPT);

1427 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)

1428 setFeature(X86::FEATURE_AVX512CD);

1429 if (HasLeaf7 && ((EBX >> 29) & 1))

1430 setFeature(X86::FEATURE_SHA);

1431 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)

1432 setFeature(X86::FEATURE_AVX512BW);

1433 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)

1434 setFeature(X86::FEATURE_AVX512VL);

1435

1436 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)

1437 setFeature(X86::FEATURE_AVX512VBMI);

1438 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)

1439 setFeature(X86::FEATURE_AVX512VBMI2);

1440 if (HasLeaf7 && ((ECX >> 8) & 1))

1441 setFeature(X86::FEATURE_GFNI);

1442 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)

1443 setFeature(X86::FEATURE_VPCLMULQDQ);

1444 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)

1445 setFeature(X86::FEATURE_AVX512VNNI);

1446 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)

1447 setFeature(X86::FEATURE_AVX512BITALG);

1448 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)

1449 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);

1450

1451 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)

1452 setFeature(X86::FEATURE_AVX5124VNNIW);

1453 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)

1454 setFeature(X86::FEATURE_AVX5124FMAPS);

1455 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)

1456 setFeature(X86::FEATURE_AVX512VP2INTERSECT);

1457

1458

1459

1460 bool HasLeaf7Subleaf1 =

1461 HasLeaf7 && EAX >= 1 &&

1462 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);

1463 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)

1464 setFeature(X86::FEATURE_AVX512BF16);

1465

1466 unsigned MaxExtLevel;

1467 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);

1468

1469 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&

1470 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);

1471 if (HasExtLeaf1 && ((ECX >> 6) & 1))

1472 setFeature(X86::FEATURE_SSE4_A);

1473 if (HasExtLeaf1 && ((ECX >> 11) & 1))

1474 setFeature(X86::FEATURE_XOP);

1475 if (HasExtLeaf1 && ((ECX >> 16) & 1))

1476 setFeature(X86::FEATURE_FMA4);

1477

1478 if (HasExtLeaf1 && ((EDX >> 29) & 1))

1479 setFeature(X86::FEATURE_64BIT);

1480}

1481

1483 unsigned MaxLeaf = 0;

1486 return "generic";

1487

1488 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;

1489 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);

1490

1491 unsigned Family = 0, Model = 0;

1493 detectX86FamilyModel(EAX, &Family, &Model);

1494 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);

1495

1496

1497

1498 unsigned Type = 0;

1499 unsigned Subtype = 0;

1500

1502

1504 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,

1505 &Subtype);

1507 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,

1508 &Subtype);

1509 }

1510

1511 if (!CPU.empty())

1512 return CPU;

1513

1514 return "generic";

1515}

1516

1517#elif defined(_M_ARM64) || defined(_M_ARM64EC)

1518

1520 constexpr char CentralProcessorKeyName[] =

1521 "HARDWARE\\DESCRIPTION\\System\\CentralProcessor";

1522

1523

1524 constexpr size_t SubKeyNameMaxSize = ARRAYSIZE(CentralProcessorKeyName) + 10;

1525

1528 char PrimaryPartKeyName[SubKeyNameMaxSize];

1529 DWORD PrimaryPartKeyNameSize = 0;

1530 HKEY CentralProcessorKey;

1531 if (RegOpenKeyExA(HKEY_LOCAL_MACHINE, CentralProcessorKeyName, 0, KEY_READ,

1532 &CentralProcessorKey) == ERROR_SUCCESS) {

1533 for (unsigned Index = 0; Index < UINT32_MAX; ++Index) {

1534 char SubKeyName[SubKeyNameMaxSize];

1535 DWORD SubKeySize = SubKeyNameMaxSize;

1536 HKEY SubKey;

1537 if ((RegEnumKeyExA(CentralProcessorKey, Index, SubKeyName, &SubKeySize,

1538 nullptr, nullptr, nullptr,

1539 nullptr) == ERROR_SUCCESS) &&

1540 (RegOpenKeyExA(CentralProcessorKey, SubKeyName, 0, KEY_READ,

1541 &SubKey) == ERROR_SUCCESS)) {

1542

1543

1545 DWORD ActualType;

1546 DWORD RegValueSize = sizeof(RegValue);

1547 if ((RegQueryValueExA(SubKey, "CP 4000", nullptr, &ActualType,

1548 (PBYTE)&RegValue,

1549 &RegValueSize) == ERROR_SUCCESS) &&

1550 (ActualType == REG_QWORD) && RegValueSize == sizeof(RegValue)) {

1551

1552

1553

1554

1555 if (PrimaryPartKeyNameSize < SubKeySize ||

1556 (PrimaryPartKeyNameSize == SubKeySize &&

1557 ::memcmp(SubKeyName, PrimaryPartKeyName, SubKeySize) > 0)) {

1558 PrimaryCpuInfo = RegValue;

1559 ::memcpy(PrimaryPartKeyName, SubKeyName, SubKeySize + 1);

1560 PrimaryPartKeyNameSize = SubKeySize;

1561 }

1564 }

1565 }

1566 RegCloseKey(SubKey);

1567 } else {

1568

1569 break;

1570 }

1571 }

1572 RegCloseKey(CentralProcessorKey);

1573 }

1574

1575 if (Values.empty()) {

1576 return "generic";

1577 }

1578

1579

1580

1582

1584}

1585

1586#elif defined(__APPLE__) && defined(__powerpc__)

1588 host_basic_info_data_t hostInfo;

1589 mach_msg_type_number_t infoCount;

1590

1591 infoCount = HOST_BASIC_INFO_COUNT;

1592 mach_port_t hostPort = mach_host_self();

1593 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,

1594 &infoCount);

1595 mach_port_deallocate(mach_task_self(), hostPort);

1596

1597 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)

1598 return "generic";

1599

1600 switch (hostInfo.cpu_subtype) {

1602 return "601";

1604 return "602";

1606 return "603";

1608 return "603e";

1610 return "603ev";

1612 return "604";

1614 return "604e";

1616 return "620";

1618 return "750";

1620 return "7400";

1622 return "7450";

1624 return "970";

1625 default:;

1626 }

1627

1628 return "generic";

1629}

1630#elif defined(__linux__) && defined(__powerpc__)

1633 StringRef Content = P ? P->getBuffer() : "";

1635}

1636#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))

1639 StringRef Content = P ? P->getBuffer() : "";

1641}

1642#elif defined(__linux__) && defined(__s390x__)

1645 StringRef Content = P ? P->getBuffer() : "";

1647}

1648#elif defined(__MVS__)

1650

1651

1652

1653 int *StartToCVTOffset = reinterpret_cast<int *>(0x10);

1654

1655

1656 int ReadValue = *StartToCVTOffset;

1657

1658 ReadValue = (ReadValue & 0x7FFFFFFF);

1659 char *CVT = reinterpret_cast<char *>(ReadValue);

1660

1661

1663

1665

1666

1667

1668 bool HaveVectorSupport = CVT[244] & 0x80;

1669 return getCPUNameFromS390Model(Id, HaveVectorSupport);

1670}

1671#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))

1672

1673

1674

1675

1676#define CPUFAMILY_UNKNOWN 0

1677#define CPUFAMILY_ARM_9 0xe73283ae

1678#define CPUFAMILY_ARM_11 0x8ff620d8

1679#define CPUFAMILY_ARM_XSCALE 0x53b005f5

1680#define CPUFAMILY_ARM_12 0xbd1b0ae9

1681#define CPUFAMILY_ARM_13 0x0cc90e64

1682#define CPUFAMILY_ARM_14 0x96077ef1

1683#define CPUFAMILY_ARM_15 0xa8511bca

1684#define CPUFAMILY_ARM_SWIFT 0x1e2d6381

1685#define CPUFAMILY_ARM_CYCLONE 0x37a09642

1686#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e

1687#define CPUFAMILY_ARM_TWISTER 0x92fb37c8

1688#define CPUFAMILY_ARM_HURRICANE 0x67ceee93

1689#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6

1690#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f

1691#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2

1692#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3

1693#define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d

1694#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea

1695#define CPUFAMILY_ARM_IBIZA 0xfa33415e

1696#define CPUFAMILY_ARM_PALMA 0x72015832

1697#define CPUFAMILY_ARM_COLL 0x2876f5b5

1698#define CPUFAMILY_ARM_LOBOS 0x5f4dea93

1699#define CPUFAMILY_ARM_DONAN 0x6f5129ac

1700#define CPUFAMILY_ARM_BRAVA 0x17d5b93a

1701#define CPUFAMILY_ARM_TAHITI 0x75d4acb9

1702#define CPUFAMILY_ARM_TUPAI 0x204526d0

1703

1706 size_t Length = sizeof(Family);

1707 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0);

1708

1709

1710

1711

1712

1713

1714

1715

1716

1717

1718 switch (Family) {

1719 case CPUFAMILY_UNKNOWN:

1720 return "generic";

1721 case CPUFAMILY_ARM_9:

1722 return "arm920t";

1723 case CPUFAMILY_ARM_11:

1724 return "arm1136jf-s";

1725 case CPUFAMILY_ARM_XSCALE:

1726 return "xscale";

1727 case CPUFAMILY_ARM_12:

1728 return "generic";

1729 case CPUFAMILY_ARM_13:

1730 return "cortex-a8";

1731 case CPUFAMILY_ARM_14:

1732 return "cortex-a9";

1733 case CPUFAMILY_ARM_15:

1734 return "cortex-a7";

1735 case CPUFAMILY_ARM_SWIFT:

1736 return "swift";

1737 case CPUFAMILY_ARM_CYCLONE:

1738 return "apple-a7";

1739 case CPUFAMILY_ARM_TYPHOON:

1740 return "apple-a8";

1741 case CPUFAMILY_ARM_TWISTER:

1742 return "apple-a9";

1743 case CPUFAMILY_ARM_HURRICANE:

1744 return "apple-a10";

1745 case CPUFAMILY_ARM_MONSOON_MISTRAL:

1746 return "apple-a11";

1747 case CPUFAMILY_ARM_VORTEX_TEMPEST:

1748 return "apple-a12";

1749 case CPUFAMILY_ARM_LIGHTNING_THUNDER:

1750 return "apple-a13";

1751 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:

1752 return "apple-m1";

1753 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE:

1754 return "apple-m2";

1755 case CPUFAMILY_ARM_EVEREST_SAWTOOTH:

1756 case CPUFAMILY_ARM_IBIZA:

1757 case CPUFAMILY_ARM_PALMA:

1758 case CPUFAMILY_ARM_LOBOS:

1759 return "apple-m3";

1760 case CPUFAMILY_ARM_COLL:

1761 return "apple-a17";

1762 case CPUFAMILY_ARM_DONAN:

1763 case CPUFAMILY_ARM_BRAVA:

1764 case CPUFAMILY_ARM_TAHITI:

1765 case CPUFAMILY_ARM_TUPAI:

1766 return "apple-m4";

1767 default:

1768

1769 return "apple-m4";

1770 }

1771}

1772#elif defined(_AIX)

1774 switch (_system_configuration.implementation) {

1775 case POWER_4:

1776 if (_system_configuration.version == PV_4_3)

1777 return "970";

1778 return "pwr4";

1779 case POWER_5:

1780 if (_system_configuration.version == PV_5)

1781 return "pwr5";

1782 return "pwr5x";

1783 case POWER_6:

1784 if (_system_configuration.version == PV_6_Compat)

1785 return "pwr6";

1786 return "pwr6x";

1787 case POWER_7:

1788 return "pwr7";

1789 case POWER_8:

1790 return "pwr8";

1791 case POWER_9:

1792 return "pwr9";

1793

1794#ifdef POWER_10

1795 case POWER_10:

1796#else

1797 case 0x40000:

1798#endif

1799 return "pwr10";

1800#ifdef POWER_11

1801 case POWER_11:

1802#else

1803 case 0x80000:

1804#endif

1805 return "pwr11";

1806 default:

1807 return "generic";

1808 }

1809}

1810#elif defined(__loongarch__)

1812

1814 __asm__("cpucfg %[prid], $zero\n\t" : [prid] "=r"(processor_id));

1815

1816 switch (processor_id & 0xf000) {

1817 case 0xc000:

1818 return "la464";

1819 case 0xd000:

1820 return "la664";

1821

1822 default:

1823 break;

1824 }

1825 return "generic";

1826}

1827#elif defined(__riscv)

1828#if defined(__linux__)

1829

1830struct RISCVHwProbe {

1831 int64_t Key;

1833};

1834#endif

1835

1837#if defined(__linux__)

1838

1839 RISCVHwProbe Query[]{{0, 0},

1840 {1, 0},

1841 {2, 0}};

1842 int Ret = syscall(258, Query,

1843 std::size(Query), 0,

1844 0, 0);

1845 if (Ret == 0) {

1847 Query[2].Value};

1849 if ( Name .empty())

1850 return Name;

1851 }

1852

1853

1855 StringRef Content = P ? P->getBuffer() : "";

1857 if ( Name .empty())

1858 return Name;

1859#endif

1860#if __riscv_xlen == 64

1861 return "generic-rv64";

1862#elif __riscv_xlen == 32

1863 return "generic-rv32";

1864#else

1865#error "Unhandled value of __riscv_xlen"

1866#endif

1867}

1868#elif defined(__sparc__)

1869#if defined(__linux__)

1872 ProcCpuinfoContent.split(Lines, '\n');

1873

1874

1876 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {

1878 Cpu = Lines[I].substr(5).ltrim("\t :");

1879 break;

1880 }

1881 }

1882

1884 .StartsWith("SuperSparc", "supersparc")

1885 .StartsWith("HyperSparc", "hypersparc")

1886 .StartsWith("SpitFire", "ultrasparc")

1887 .StartsWith("BlackBird", "ultrasparc")

1889 .StartsWith("Hummingbird", "ultrasparc")

1890 .StartsWith("Cheetah", "ultrasparc3")

1891 .StartsWith("Jalapeno", "ultrasparc3")

1892 .StartsWith("Jaguar", "ultrasparc3")

1893 .StartsWith("Panther", "ultrasparc3")

1894 .StartsWith("Serrano", "ultrasparc3")

1895 .StartsWith("UltraSparc T1", "niagara")

1896 .StartsWith("UltraSparc T2", "niagara2")

1897 .StartsWith("UltraSparc T3", "niagara3")

1898 .StartsWith("UltraSparc T4", "niagara4")

1899 .StartsWith("UltraSparc T5", "niagara4")

1901

1902 .StartsWith("SPARC-M7", "niagara4" )

1903 .StartsWith("SPARC-S7", "niagara4" )

1904 .StartsWith("SPARC-M8", "niagara4" )

1906}

1907#endif

1908

1910#if defined(__linux__)

1912 StringRef Content = P ? P->getBuffer() : "";

1914#elif defined(__sun__) && defined(__svr4__)

1915 char *buf = NULL;

1916 kstat_ctl_t *kc;

1917 kstat_t *ksp;

1918 kstat_named_t *brand = NULL;

1919

1920 kc = kstat_open();

1921 if (kc != NULL) {

1922 ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL);

1923 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&

1924 ksp->ks_type == KSTAT_TYPE_NAMED)

1925 brand =

1926 (kstat_named_t *)kstat_data_lookup(ksp, const_cast<char *>("brand"));

1927 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)

1928 buf = KSTAT_NAMED_STR_PTR(brand);

1929 }

1930 kstat_close(kc);

1931

1933 .Case("TMS390S10", "supersparc")

1934 .Case("TMS390Z50", "supersparc")

1935 .Case("TMS390Z55",

1936 "supersparc")

1937 .Case("MB86904", "supersparc")

1938 .Case("MB86907", "supersparc")

1939 .Case("RT623", "hypersparc")

1940 .Case("RT625", "hypersparc")

1941 .Case("RT626", "hypersparc")

1942 .Case("UltraSPARC-I", "ultrasparc")

1943 .Case("UltraSPARC-II", "ultrasparc")

1944 .Case("UltraSPARC-IIe", "ultrasparc")

1945 .Case("UltraSPARC-IIi", "ultrasparc")

1946 .Case("SPARC64-III", "ultrasparc")

1947 .Case("SPARC64-IV", "ultrasparc")

1948 .Case("UltraSPARC-III", "ultrasparc3")

1949 .Case("UltraSPARC-III+", "ultrasparc3")

1950 .Case("UltraSPARC-IIIi", "ultrasparc3")

1951 .Case("UltraSPARC-IIIi+", "ultrasparc3")

1952 .Case("UltraSPARC-IV", "ultrasparc3")

1953 .Case("UltraSPARC-IV+", "ultrasparc3")

1954 .Case("SPARC64-V", "ultrasparc3")

1955 .Case("SPARC64-VI", "ultrasparc3")

1956 .Case("SPARC64-VII", "ultrasparc3")

1957 .Case("UltraSPARC-T1", "niagara")

1958 .Case("UltraSPARC-T2", "niagara2")

1959 .Case("UltraSPARC-T2", "niagara2")

1960 .Case("UltraSPARC-T2+", "niagara2")

1961 .Case("SPARC-T3", "niagara3")

1962 .Case("SPARC-T4", "niagara4")

1963 .Case("SPARC-T5", "niagara4")

1964

1965 .Case("SPARC-M7", "niagara4" )

1966 .Case("SPARC-S7", "niagara4" )

1967 .Case("SPARC-M8", "niagara4" )

1969#else

1970 return "generic";

1971#endif

1972}

1973#else

1975namespace llvm {

1976namespace sys {

1978namespace x86 {

1979

1983

1984}

1985}

1986}

1987}

1988#endif

1989

1990#if (defined(__i386__) || defined(_M_IX86) || defined(__x86_64__) || \

1991 defined(_M_X64)) && \

1992 !defined(_M_ARM64EC)

1994 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;

1995 unsigned MaxLevel;

1997

1998 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)

1999 return Features;

2000

2001 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);

2002

2003 Features["cx8"] = (EDX >> 8) & 1;

2004 Features["cmov"] = (EDX >> 15) & 1;

2005 Features["mmx"] = (EDX >> 23) & 1;

2006 Features["fxsr"] = (EDX >> 24) & 1;

2007 Features["sse"] = (EDX >> 25) & 1;

2008 Features["sse2"] = (EDX >> 26) & 1;

2009

2010 Features["sse3"] = (ECX >> 0) & 1;

2011 Features["pclmul"] = (ECX >> 1) & 1;

2012 Features["ssse3"] = (ECX >> 9) & 1;

2013 Features["cx16"] = (ECX >> 13) & 1;

2014 Features["sse4.1"] = (ECX >> 19) & 1;

2015 Features["sse4.2"] = (ECX >> 20) & 1;

2016 Features["crc32"] = Features["sse4.2"];

2017 Features["movbe"] = (ECX >> 22) & 1;

2018 Features["popcnt"] = (ECX >> 23) & 1;

2019 Features["aes"] = (ECX >> 25) & 1;

2020 Features["rdrnd"] = (ECX >> 30) & 1;

2021

2022

2023

2024

2025 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);

2026 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);

2027#if defined(__APPLE__)

2028

2029

2030

2031 bool HasAVX512Save = true;

2032#else

2033

2034 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);

2035#endif

2036

2037 const unsigned AMXBits = (1 << 17) | (1 << 18);

2038 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);

2039

2040 Features["avx"] = HasAVXSave;

2041 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;

2042

2043 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;

2044 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;

2045

2046 unsigned MaxExtLevel;

2047 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);

2048

2049 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&

2050 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);

2051 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);

2052 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);

2053 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);

2054 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);

2055 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;

2056 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);

2057 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;

2058 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);

2059 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);

2060

2061 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);

2062

2063

2064

2065 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&

2066 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);

2067 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);

2068 Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);

2069 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);

2070

2071 bool HasExtLeaf21 = MaxExtLevel >= 0x80000021 &&

2072 !getX86CpuIDAndInfo(0x80000021, &EAX, &EBX, &ECX, &EDX);

2073

2074 Features["prefetchi"] = HasExtLeaf21 && ((EAX >> 20) & 1);

2075

2076 bool HasLeaf7 =

2077 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);

2078

2079 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);

2080 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);

2081 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);

2082

2083 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;

2084 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);

2085 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);

2086 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);

2087

2088 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;

2089 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;

2090 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);

2091 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);

2092 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;

2093 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);

2094 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);

2095 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;

2096 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);

2097 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;

2098 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;

2099

2100 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;

2101 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);

2102 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);

2103 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;

2104 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);

2105 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);

2106 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;

2107 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;

2108 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;

2109 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;

2110 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;

2111 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);

2112 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1);

2113 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);

2114 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);

2115 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);

2116 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);

2117

2118 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1);

2119 Features["avx512vp2intersect"] =

2120 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;

2121 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);

2122 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);

2123

2124

2125

2126

2127

2128

2129

2130

2131

2132

2133 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);

2134 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;

2135 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;

2136 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;

2137 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;

2138

2139

2140 bool HasLeaf7Subleaf1 =

2141 HasLeaf7 && EAX >= 1 &&

2142 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);

2143 Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);

2144 Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);

2145 Features["sm4"] = HasLeaf7Subleaf1 && ((EAX >> 2) & 1);

2146 Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);

2147 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;

2148 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;

2149 Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;

2150 Features["cmpccxadd"] = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);

2151 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);

2152 Features["avxifma"] = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;

2153 Features["movrs"] = HasLeaf7Subleaf1 && ((EAX >> 31) & 1);

2154 Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;

2155 Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;

2156 Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;

2157 Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;

2158 Features["prefetchi"] |= HasLeaf7Subleaf1 && ((EDX >> 14) & 1);

2159 Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);

2160 bool HasAVX10 = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);

2161 bool HasAPXF = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);

2162 Features["egpr"] = HasAPXF;

2163 Features["push2pop2"] = HasAPXF;

2164 Features["ppx"] = HasAPXF;

2165 Features["ndd"] = HasAPXF;

2166 Features["ccmp"] = HasAPXF;

2167 Features["nf"] = HasAPXF;

2168 Features["cf"] = HasAPXF;

2169 Features["zu"] = HasAPXF;

2170

2171 bool HasLeafD = MaxLevel >= 0xd &&

2172 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);

2173

2174

2175 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;

2176 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;

2177 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;

2178

2179 bool HasLeaf14 = MaxLevel >= 0x14 &&

2180 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);

2181

2182 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);

2183

2184 bool HasLeaf19 =

2185 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);

2186 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);

2187

2188 bool HasLeaf1E = MaxLevel >= 0x1e &&

2189 !getX86CpuIDAndInfoEx(0x1e, 0x1, &EAX, &EBX, &ECX, &EDX);

2190 Features["amx-fp8"] = HasLeaf1E && ((EAX >> 4) & 1) && HasAMXSave;

2191 Features["amx-tf32"] = HasLeaf1E && ((EAX >> 6) & 1) && HasAMXSave;

2192 Features["amx-avx512"] = HasLeaf1E && ((EAX >> 7) & 1) && HasAMXSave;

2193 Features["amx-movrs"] = HasLeaf1E && ((EAX >> 8) & 1) && HasAMXSave;

2194

2195 bool HasLeaf24 =

2196 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);

2197

2198 int AVX10Ver = HasLeaf24 && (EBX & 0xff);

2199 Features["avx10.1"] = HasAVX10 && AVX10Ver >= 1;

2200 Features["avx10.2"] = HasAVX10 && AVX10Ver >= 2;

2201

2202 return Features;

2203}

2204#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))

2208 if ()

2209 return Features;

2210

2212 P->getBuffer().split(Lines, '\n');

2213

2215

2216

2217 for (unsigned I = 0, E = Lines.size(); I != E; ++I)

2219 Lines[I].split(CPUFeatures, ' ');

2220 break;

2221 }

2222

2223#if defined(__aarch64__)

2224

2225

2226 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };

2228#endif

2229

2230 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {

2232#if defined(__aarch64__)

2233 .Case("asimd", "neon")

2234 .Case("fp", "fp-armv8")

2235 .Case("crc32", "crc")

2236 .Case("atomics", "lse")

2237 .Case("sha3", "sha3")

2238 .Case("sm4", "sm4")

2239 .Case("sve", "sve")

2240 .Case("sve2", "sve2")

2241 .Case("sveaes", "sve-aes")

2242 .Case("svesha3", "sve-sha3")

2243 .Case("svesm4", "sve-sm4")

2244#else

2245 .Case("half", "fp16")

2246 .Case("neon", "neon")

2247 .Case("vfpv3", "vfp3")

2248 .Case("vfpv3d16", "vfp3d16")

2249 .Case("vfpv4", "vfp4")

2250 .Case("idiva", "hwdiv-arm")

2251 .Case("idivt", "hwdiv")

2252#endif

2254

2255#if defined(__aarch64__)

2256

2257

2258 if (CPUFeatures[I] == "aes")

2259 crypto |= CAP_AES;

2260 else if (CPUFeatures[I] == "pmull")

2261 crypto |= CAP_PMULL;

2262 else if (CPUFeatures[I] == "sha1")

2263 crypto |= CAP_SHA1;

2264 else if (CPUFeatures[I] == "sha2")

2265 crypto |= CAP_SHA2;

2266#endif

2267

2268 if (LLVMFeatureStr != "")

2269 Features[LLVMFeatureStr] = true;

2270 }

2271

2272#if defined(__aarch64__)

2273

2274

2275

2276 uint32_t Aes = CAP_AES | CAP_PMULL;

2277 uint32_t Sha2 = CAP_SHA1 | CAP_SHA2;

2278 Features["aes"] = (crypto & Aes) == Aes;

2279 Features["sha2"] = (crypto & Sha2) == Sha2;

2280

2281

2282

2283

2284 if (!Features.contains("sve"))

2285 Features["sve"] = false;

2286#endif

2287

2288 return Features;

2289}

2290#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64) || \

2291 defined(__arm64ec__) || defined(_M_ARM64EC))

2292#ifndef PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE

2293#define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE 43

2294#endif

2295#ifndef PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE

2296#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE 44

2297#endif

2298#ifndef PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE

2299#define PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE 45

2300#endif

2301#ifndef PF_ARM_SVE_INSTRUCTIONS_AVAILABLE

2302#define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE 46

2303#endif

2304#ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE

2305#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE 47

2306#endif

2307#ifndef PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE

2308#define PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE 50

2309#endif

2310#ifndef PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE

2311#define PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE 55

2312#endif

2313#ifndef PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE

2314#define PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE 56

2315#endif

2316#ifndef PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE

2317#define PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE 57

2318#endif

2319#ifndef PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE

2320#define PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE 58

2321#endif

2322#ifndef PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE

2323#define PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE 59

2324#endif

2327

2328

2329 Features["crc"] =

2330 IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE);

2331 Features["lse"] =

2332 IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE);

2333 Features["dotprod"] =

2334 IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE);

2335 Features["jsconv"] =

2336 IsProcessorFeaturePresent(PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE);

2337 Features["rcpc"] =

2338 IsProcessorFeaturePresent(PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE);

2339 Features["sve"] =

2340 IsProcessorFeaturePresent(PF_ARM_SVE_INSTRUCTIONS_AVAILABLE);

2341 Features["sve2"] =

2342 IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE);

2343 Features["sve-aes"] =

2344 IsProcessorFeaturePresent(PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE);

2345 Features["sve-sha3"] =

2346 IsProcessorFeaturePresent(PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE);

2347 Features["sve-sm4"] =

2348 IsProcessorFeaturePresent(PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE);

2349 Features["f32mm"] =

2350 IsProcessorFeaturePresent(PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE);

2351 Features["f64mm"] =

2352 IsProcessorFeaturePresent(PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE);

2353 Features["i8mm"] =

2354 IsProcessorFeaturePresent(PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE);

2355

2356

2357 bool TradCrypto =

2358 IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE);

2359 Features["aes"] = TradCrypto;

2360 Features["sha2"] = TradCrypto;

2361

2362 return Features;

2363}

2364#elif defined(__linux__) && defined(__loongarch__)

2365#include <sys/auxv.h>

2367 unsigned long hwcap = getauxval(AT_HWCAP);

2368 bool HasFPU = hwcap & (1UL << 3);

2369 uint32_t cpucfg2 = 0x2, cpucfg3 = 0x3;

2370 __asm__("cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2] "+r"(cpucfg2));

2371 __asm__("cpucfg %[cpucfg3], %[cpucfg3]\n\t" : [cpucfg3] "+r"(cpucfg3));

2372

2374

2375 Features["f"] = HasFPU && (cpucfg2 & (1U << 1));

2376 Features["d"] = HasFPU && (cpucfg2 & (1U << 2));

2377

2378 Features["lsx"] = hwcap & (1UL << 4);

2379 Features["lasx"] = hwcap & (1UL << 5);

2380 Features["lvz"] = hwcap & (1UL << 9);

2381

2382 Features["frecipe"] = cpucfg2 & (1U << 25);

2383 Features["div32"] = cpucfg2 & (1U << 26);

2384 Features["lam-bh"] = cpucfg2 & (1U << 27);

2385 Features["lamcas"] = cpucfg2 & (1U << 28);

2386 Features["scq"] = cpucfg2 & (1U << 30);

2387

2388 Features["ld-seq-sa"] = cpucfg3 & (1U << 23);

2389

2390

2391

2392 return Features;

2393}

2394#elif defined(__linux__) && defined(__riscv)

2396 RISCVHwProbe Query[]{{3, 0},

2397 {4, 0},

2398 {9, 0}};

2399 int Ret = syscall(258, Query,

2400 std::size(Query), 0,

2401 0, 0);

2402 if (Ret != 0)

2403 return {};

2404

2406 uint64_t BaseMask = Query[0].Value;

2407

2408 if (BaseMask & 1) {

2409 Features["i"] = true;

2410 Features["m"] = true;

2411 Features["a"] = true;

2412 }

2413

2414 uint64_t ExtMask = Query[1].Value;

2415 Features["f"] = ExtMask & (1 << 0);

2416 Features["d"] = ExtMask & (1 << 0);

2417 Features["c"] = ExtMask & (1 << 1);

2418 Features["v"] = ExtMask & (1 << 2);

2419 Features["zba"] = ExtMask & (1 << 3);

2420 Features["zbb"] = ExtMask & (1 << 4);

2421 Features["zbs"] = ExtMask & (1 << 5);

2422 Features["zicboz"] = ExtMask & (1 << 6);

2423 Features["zbc"] = ExtMask & (1 << 7);

2424 Features["zbkb"] = ExtMask & (1 << 8);

2425 Features["zbkc"] = ExtMask & (1 << 9);

2426 Features["zbkx"] = ExtMask & (1 << 10);

2427 Features["zknd"] = ExtMask & (1 << 11);

2428 Features["zkne"] = ExtMask & (1 << 12);

2429 Features["zknh"] = ExtMask & (1 << 13);

2430 Features["zksed"] = ExtMask & (1 << 14);

2431 Features["zksh"] = ExtMask & (1 << 15);

2432 Features["zkt"] = ExtMask & (1 << 16);

2433 Features["zvbb"] = ExtMask & (1 << 17);

2434 Features["zvbc"] = ExtMask & (1 << 18);

2435 Features["zvkb"] = ExtMask & (1 << 19);

2436 Features["zvkg"] = ExtMask & (1 << 20);

2437 Features["zvkned"] = ExtMask & (1 << 21);

2438 Features["zvknha"] = ExtMask & (1 << 22);

2439 Features["zvknhb"] = ExtMask & (1 << 23);

2440 Features["zvksed"] = ExtMask & (1 << 24);

2441 Features["zvksh"] = ExtMask & (1 << 25);

2442 Features["zvkt"] = ExtMask & (1 << 26);

2443 Features["zfh"] = ExtMask & (1 << 27);

2444 Features["zfhmin"] = ExtMask & (1 << 28);

2445 Features["zihintntl"] = ExtMask & (1 << 29);

2446 Features["zvfh"] = ExtMask & (1 << 30);

2447 Features["zvfhmin"] = ExtMask & (1ULL << 31);

2448 Features["zfa"] = ExtMask & (1ULL << 32);

2449 Features["ztso"] = ExtMask & (1ULL << 33);

2450 Features["zacas"] = ExtMask & (1ULL << 34);

2451 Features["zicond"] = ExtMask & (1ULL << 35);

2452 Features["zihintpause"] =

2453 ExtMask & (1ULL << 36);

2454 Features["zve32x"] = ExtMask & (1ULL << 37);

2455 Features["zve32f"] = ExtMask & (1ULL << 38);

2456 Features["zve64x"] = ExtMask & (1ULL << 39);

2457 Features["zve64f"] = ExtMask & (1ULL << 40);

2458 Features["zve64d"] = ExtMask & (1ULL << 41);

2459 Features["zimop"] = ExtMask & (1ULL << 42);

2460 Features["zca"] = ExtMask & (1ULL << 43);

2461 Features["zcb"] = ExtMask & (1ULL << 44);

2462 Features["zcd"] = ExtMask & (1ULL << 45);

2463 Features["zcf"] = ExtMask & (1ULL << 46);

2464 Features["zcmop"] = ExtMask & (1ULL << 47);

2465 Features["zawrs"] = ExtMask & (1ULL << 48);

2466

2467

2468

2469

2470

2471 if (Query[2].Key != -1 &&

2472 Query[2].Value == 3)

2473 Features["unaligned-scalar-mem"] = true;

2474

2475 return Features;

2476}

2477#else

2479#endif

2480

2481#if __APPLE__

2482

2484#if defined(__arm__)

2486 T.setArchName("arm");

2487#elif defined(__arm64e__)

2489 T.setArchName("arm64e");

2490#elif defined(__aarch64__)

2492 T.setArchName("arm64");

2493#elif defined(__x86_64h__)

2495 T.setArchName("x86_64h");

2496#elif defined(__x86_64__)

2498 T.setArchName("x86_64");

2499#elif defined(__i386__)

2501 T.setArchName("i386");

2502#elif defined(__powerpc__)

2504 T.setArchName("powerpc");

2505#else

2506# error "Unimplemented host arch fixup"

2507#endif

2508 return T;

2509}

2510#endif

2511

2513 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);

2515

2516#if __APPLE__

2517

2518

2519 PT = withHostArch(PT);

2520#endif

2521

2522 if (sizeof(void *) == 8 && PT.isArch32Bit())

2524 if (sizeof(void *) == 4 && PT.isArch64Bit())

2526

2527 return PT.str();

2528}

2529

2531#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO

2533 if (CPU == "generic")

2534 CPU = "(unknown)";

2536 << " Host CPU: " << CPU << '\n';

2537#endif

2538}

This file defines the StringMap class.

This file implements methods to test, set and extract typed bits from packed unsigned integers.

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

StringRef getHostCPUNameForARMFromComponents(StringRef Implementer, StringRef Hardware, StringRef Part, ArrayRef< StringRef > Parts, function_ref< unsigned()> GetVariant)

Definition Host.cpp:174

static std::unique_ptr< llvm::MemoryBuffer > getProcCpuinfoContent()

Definition Host.cpp:74

Merge contiguous icmps into a memcmp

This file defines the SmallVector class.

This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Represents either an error or a value T.

static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)

Read all of the specified file into a MemoryBuffer as a stream (i.e.

reference emplace_back(ArgTypes &&... Args)

void reserve(size_type N)

iterator erase(const_iterator CI)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...

bool contains(StringRef Key) const

contains - Return true if the element is in the map, false otherwise.

StringRef - Represent a constant reference to a string, i.e.

std::pair< StringRef, StringRef > split(char Separator) const

Split into two substrings around the first occurrence of a separator character.

static constexpr size_t npos

bool getAsInteger(unsigned Radix, T &Result) const

Parse the current string as an integer of the specified radix.

constexpr StringRef substr(size_t Start, size_t N=npos) const

Return a reference to the substring from [Start, Start + N).

const char * const_iterator

StringRef ltrim(char Char) const

Return string with consecutive Char characters starting from the the left removed.

bool ends_with(StringRef Suffix) const

Check if this string ends with the given Suffix.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

StringSwitch & StartsWith(StringLiteral S, T Value)

Triple - Helper class for working with autoconf configuration names.

LLVM_ABI llvm::Triple get32BitArchVariant() const

Form a triple with a 32-bit variant of the current architecture.

LLVM_ABI llvm::Triple get64BitArchVariant() const

Form a triple with a 64-bit variant of the current architecture.

static LLVM_ABI std::string normalize(StringRef Str, CanonicalForm Form=CanonicalForm::ANY)

Turn an arbitrary machine specification into the canonical triple form (or something sensible that th...

const std::string & str() const

LLVM_ABI bool isArch64Bit() const

Test whether the architecture is 64-bit.

LLVM_ABI bool isArch32Bit() const

Test whether the architecture is 32-bit.

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

An efficient, type-erasing, non-owning reference to a callable.

This class implements an extremely fast bulk output stream that can only output to a stream.

@ CPU_SUBTYPE_POWERPC_970

@ CPU_SUBTYPE_POWERPC_604e

@ CPU_SUBTYPE_POWERPC_603e

@ CPU_SUBTYPE_POWERPC_7400

@ CPU_SUBTYPE_POWERPC_604

@ CPU_SUBTYPE_POWERPC_750

@ CPU_SUBTYPE_POWERPC_601

@ CPU_SUBTYPE_POWERPC_620

@ CPU_SUBTYPE_POWERPC_603ev

@ CPU_SUBTYPE_POWERPC_603

@ CPU_SUBTYPE_POWERPC_7450

@ CPU_SUBTYPE_POWERPC_602

LLVM_ABI StringRef getCPUNameFromCPUModel(const CPUModel &Model)

Helper functions to extract CPU details from CPUID on x86.

LLVM_ABI VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)

Returns the host CPU's vendor.

Definition Host.cpp:1980

LLVM_ABI StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)

LLVM_ABI StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)

Definition Host.cpp:505

LLVM_ABI StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)

Helper functions to extract HostCPUName from /proc/cpuinfo on linux.

Definition Host.cpp:89

LLVM_ABI StringRef getHostCPUNameForBPF()

Definition Host.cpp:567

LLVM_ABI StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)

Definition Host.cpp:394

LLVM_ABI StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)

Definition Host.cpp:546

LLVM_ABI StringMap< bool, MallocAllocator > getHostCPUFeatures()

getHostCPUFeatures - Get the LLVM names for the host CPU features.

Definition Host.cpp:2478

LLVM_ABI StringRef getHostCPUName()

getHostCPUName - Get the LLVM name for the host CPU.

Definition Host.cpp:1974

LLVM_ABI void printDefaultTargetAndDetectedCPU(raw_ostream &OS)

This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...

Definition Host.cpp:2530

LLVM_ABI std::string getDefaultTargetTriple()

getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...

LLVM_ABI std::string getProcessTriple()

getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...

Definition Host.cpp:2512

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

std::string utohexstr(uint64_t X, bool LowerCase=false, unsigned Width=0)

int64_t decodePackedBCD(const uint8_t *Ptr, size_t ByteLen, bool IsSigned=true)

auto unique(Range &&R, Predicate P)

void sort(IteratorTy Start, IteratorTy End)

LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

Describes an element of a Bitfield.

static Bitfield::Type get(StorageType Packed)

Unpacks the field from the Packed value.