LLVM: include/llvm/MCA/Stages/InOrderIssueStage.h Source File (original) (raw)
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14#ifndef LLVM_MCA_STAGES_INORDERISSUESTAGE_H
15#define LLVM_MCA_STAGES_INORDERISSUESTAGE_H
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21
22namespace llvm {
23namespace mca {
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50 void update(const InstRef &Inst, unsigned Cycles, StallKind SK);
52};
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54class InOrderIssueStage final : public Stage {
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65 unsigned NumIssued;
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72 unsigned CarryOver;
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75 unsigned Bandwidth;
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80 unsigned LastWriteBackCycle;
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82 InOrderIssueStage(const InOrderIssueStage &Other) = delete;
83 InOrderIssueStage &operator=(const InOrderIssueStage &Other) = delete;
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88 bool canExecute(const InstRef &IR);
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94 void updateIssuedInst();
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97 void updateCarriedOver();
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101 void notifyStallEvent();
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103 void notifyInstructionIssued(const InstRef &IR,
105 void notifyInstructionDispatched(const InstRef &IR, unsigned Ops,
107 void notifyInstructionExecuted(const InstRef &IR);
108 void notifyInstructionRetired(const InstRef &IR,
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112 void retireInstruction(InstRef &IR);
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114public:
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124};
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126}
127}
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129#endif
This file defines the base class CustomBehaviour which can be inherited from by specific targets (ex.
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
Legalize the Machine IR a function s Machine IR
This file contains abstract class SourceMgr and the default implementation, CircularSourceMgr.
The classes here represent processor resource units and their management strategy.
This file defines a stage.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Lightweight error class with error context and mandatory checking.
Generic base class for all target subtargets.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
Error cycleEnd() override
Called once at the end of each cycle.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
bool isAvailable(const InstRef &) const override
Returns true if it can execute IR during this cycle.
unsigned getIssueWidth() const
Error cycleStart() override
Called once at the start of each cycle.
An InstRef contains both a SourceMgr index and Instruction pair.
Abstract base interface for LS (load/store) units in llvm-mca.
Manages hardware register files, and tracks register definitions for register renaming purposes.
This is an optimization pass for GlobalISel generic memory operations.
Definition InOrderIssueStage.h:27
StallKind getStallKind() const
Definition InOrderIssueStage.h:43
InstRef & getInstruction()
Definition InOrderIssueStage.h:46
const InstRef & getInstruction() const
Definition InOrderIssueStage.h:45
unsigned CyclesLeft
Definition InOrderIssueStage.h:38
StallKind Kind
Definition InOrderIssueStage.h:39
StallKind
Definition InOrderIssueStage.h:28
@ REGISTER_DEPS
Definition InOrderIssueStage.h:30
@ CUSTOM_STALL
Definition InOrderIssueStage.h:34
@ DEFAULT
Definition InOrderIssueStage.h:29
@ DELAY
Definition InOrderIssueStage.h:32
@ DISPATCH
Definition InOrderIssueStage.h:31
@ LOAD_STORE
Definition InOrderIssueStage.h:33
unsigned getCyclesLeft() const
Definition InOrderIssueStage.h:44
void update(const InstRef &Inst, unsigned Cycles, StallKind SK)
InstRef IR
Definition InOrderIssueStage.h:37
bool isValid() const
Definition InOrderIssueStage.h:48