LLVM: lib/Target/VE/LVLGen.cpp Source File (original) (raw)
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15using namespace llvm;
16
17#define DEBUG_TYPE "lvl-gen"
18
19namespace {
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24 static char ID;
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30 int getVLIndex(unsigned Opcode);
31};
32char LVLGen::ID = 0;
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34}
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38int LVLGen::getVLIndex(unsigned Opcode) {
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45 return -1;
46}
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50unsigned LVLGen::getVL(const MachineInstr &MI) {
51 int Index = getVLIndex(MI.getOpcode());
52 if (Index >= 0)
53 return MI.getOperand(Index).getReg();
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55 return VE::NoRegister;
56}
57
58bool LVLGen::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
59#define RegName(no) \
60 (MBB.getParent()->getSubtarget().getRegisterInfo()->getName(no))
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63 bool HasRegForVL = false;
64 unsigned RegForVL;
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76 if (Reg != VE::NoRegister) {
81 << (HasRegForVL ? RegName(RegForVL) : "unknown")
82 << ". ");
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84 if (!HasRegForVL || RegForVL != Reg) {
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87 LLVM_DEBUG(dbgs() << "Generate a LVL instruction to load "
90 HasRegForVL = true;
91 RegForVL = Reg;
93 } else {
95 }
96 }
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99 if (HasRegForVL) {
100 if (MI->definesRegister(RegForVL, TRI) ||
101 MI->modifiesRegister(RegForVL, TRI) ||
102 MI->killsRegister(RegForVL, TRI) || MI->isCall()) {
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106 HasRegForVL = false;
107 }
108 }
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110 ++I;
111 }
113}
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115bool LVLGen::runOnMachineFunction(MachineFunction &F) {
116 LLVM_DEBUG(dbgs() << "********** Begin LVLGen **********\n");
117 LLVM_DEBUG(dbgs() << "********** Function: " << F.getName() << '\n');
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122 const VESubtarget &Subtarget = F.getSubtarget();
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126 for (MachineBasicBlock &MBB : F)
127 Changed |= runOnMachineBasicBlock(MBB);
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132 }
133 LLVM_DEBUG(dbgs() << "********** End LVLGen **********\n");
135}
const TargetInstrInfo & TII
Register const TargetRegisterInfo * TRI
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
MachineInstrBundleIterator< MachineInstr > iterator
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const VEInstrInfo * getInstrInfo() const override
const VERegisterInfo * getRegisterInfo() const override
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass * createLVLGenPass()
Definition LVLGen.cpp:36
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.