LanaiDisassembler.cpp Source File (original) (raw)

25using namespace llvm;

33}

39}

73#include "LanaiGenDisassemblerTables.inc"

78 if (Bytes.size() < 4) {

81 }

85 (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);

88}

93 int PqShift = -1;

95 PqShift = 16;

97 PqShift = 10;

98 else if (isRRMOpcode(Instr.getOpcode())) {

99 PqShift = 16;

100

101 AluOp = (Insn >> 8) & 0x7;

102 if (AluOp == 7)

103

104

105 AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1);

106 }

107

108 if (PqShift != -1) {

109 unsigned PQ = (Insn >> PqShift) & 0x3;

110 switch (PQ) {

111 case 0x0:

112 if (Instr.getOperand(2).isReg()) {

113 Instr.getOperand(2).setReg(Lanai::R0);

114 }

115 if (Instr.getOperand(2).isImm())

116 Instr.getOperand(2).setImm(0);

117 break;

118 case 0x1:

120 break;

121 case 0x2:

122 break;

123 case 0x3:

125 break;

126 }

128 }

129}

130

136

138

141

142

143 Result =

144 decodeInstruction(DecoderTableLanai32, Instr, Insn, Address, this, STI);

145

149 return Result;

150 }

151

153}

154

156 Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP,

157 Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,

158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,

159 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,

160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,

161 Lanai::R30, Lanai::R31};

162

166 if (RegNo > 31)

168

172}

173

177

178

183

185}

186

190

191

196

198}

199

203

204

209

211}

212

218 Width, 0);

219}

220

224 Decoder))

227}

228

234

236}

237

245}

SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn

static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const MCDisassembler *Decoder)

tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...

static const uint16_t GPRDecoderTable[]

#define LLVM_EXTERNAL_VISIBILITY

static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

MCDisassembler::DecodeStatus DecodeStatus

static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn)

static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiDisassembler()

static MCDisassembler * createLanaiDisassembler(const Target &, const MCSubtargetInfo &STI, MCContext &Ctx)

static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)

MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override

Returns the disassembly of a single instruction.

Context object for machine code objects.

Superclass for all disassemblers.

bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const

const MCSubtargetInfo & STI

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

Generic base class for all target subtargets.

Wrapper class representing virtual and physical registers.

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

static unsigned makePostOp(unsigned AluOp)

static unsigned makePreOp(unsigned AluOp)

This is an optimization pass for GlobalISel generic memory operations.

static bool isRMOpcode(unsigned Opcode)

Target & getTheLanaiTarget()

static bool isRRMOpcode(unsigned Opcode)

static bool isSPLSOpcode(unsigned Opcode)

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.