LanaiDisassembler.cpp Source File (original) (raw)

28#define DEBUG_TYPE "lanai-disassembler"

30using namespace llvm;

53 Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP,

54 Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,

55 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,

56 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,

57 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,

58 Lanai::R30, Lanai::R31

59};

65 if (RegNo > 31)

71}

78 unsigned Register = (Insn >> 18) & 0x1f;

80 unsigned Offset = (Insn & 0xffff);

84}

91 unsigned Register = (Insn >> 15) & 0x1f;

93 Register = (Insn >> 10) & 0x1f;

97}

102

103

104 unsigned Register = (Insn >> 12) & 0x1f;

106 unsigned Offset = (Insn & 0x3ff);

108

110}

111

119

127

131 unsigned Offset = (Insn & 0xffff);

133

135}

136

145

146#include "LanaiGenDisassemblerTables.inc"

147

150

151 if (Bytes.size() < 4) {

154 }

155

156

157 Insn =

158 (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);

159

161}

162

165

166 int PqShift = -1;

168 PqShift = 16;

170 PqShift = 10;

171 else if (isRRMOpcode(Instr.getOpcode())) {

172 PqShift = 16;

173

174 AluOp = (Insn >> 8) & 0x7;

175 if (AluOp == 7)

176

177

178 AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1);

179 }

180

181 if (PqShift != -1) {

182 unsigned PQ = (Insn >> PqShift) & 0x3;

183 switch (PQ) {

184 case 0x0:

185 if (Instr.getOperand(2).isReg()) {

186 Instr.getOperand(2).setReg(Lanai::R0);

187 }

188 if (Instr.getOperand(2).isImm())

189 Instr.getOperand(2).setImm(0);

190 break;

191 case 0x1:

193 break;

194 case 0x2:

195 break;

196 case 0x3:

198 break;

199 }

201 }

202}

203

209

211

214

215

216 Result =

217 decodeInstruction(DecoderTableLanai32, Instr, Insn, Address, this, STI);

218

222 return Result;

223 }

224

226}

MCDisassembler::DecodeStatus DecodeStatus

static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const MCDisassembler *Decoder)

tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...

static const uint16_t GPRDecoderTable[]

#define LLVM_EXTERNAL_VISIBILITY

static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition LanaiDisassembler.cpp:86

static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition LanaiDisassembler.cpp:99

static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn)

Definition LanaiDisassembler.cpp:163

static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition LanaiDisassembler.cpp:73

static MCDisassembler * createLanaiDisassembler(const Target &, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition LanaiDisassembler.cpp:35

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiDisassembler()

Definition LanaiDisassembler.cpp:42

static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition LanaiDisassembler.cpp:128

static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const MCDisassembler *Decoder)

Definition LanaiDisassembler.cpp:137

static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition LanaiDisassembler.cpp:120

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)

Definition LanaiDisassembler.cpp:48

MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override

Returns the disassembly of a single instruction.

Definition LanaiDisassembler.cpp:205

Context object for machine code objects.

Superclass for all disassemblers.

MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)

bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const

const MCSubtargetInfo & STI

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

Generic base class for all target subtargets.

Wrapper class representing virtual and physical registers.

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

static unsigned makePostOp(unsigned AluOp)

static unsigned makePreOp(unsigned AluOp)

This is an optimization pass for GlobalISel generic memory operations.

static bool isRMOpcode(unsigned Opcode)

Target & getTheLanaiTarget()

static bool isRRMOpcode(unsigned Opcode)

static bool isSPLSOpcode(unsigned Opcode)

constexpr int32_t SignExtend32(uint32_t X)

Sign-extend the number in the bottom B bits of X to a 32-bit integer.

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.