LanaiInstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H

14#define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H

20#define GET_INSTRINFO_HEADER

21#include "LanaiGenInstrInfo.inc"

23namespace llvm {

25class LanaiSubtarget;

30public:

37 return RegisterInfo;

38 }

44 int &FrameIndex) const override;

47 int &FrameIndex) const override;

50 int &FrameIndex) const override;

54 Register SourceRegister, bool KillSource,

55 bool RenamableDest = false,

56 bool RenamableSrc = false) const override;

60 Register SourceRegister, bool IsKill, int FrameIndex,

66 Register DestinationRegister, int FrameIndex,

83 std::pair<unsigned, unsigned>

92 bool AllowModify) const override;

95 int *BytesRemoved = nullptr) const override;

101 Register &SrcReg2, int64_t &CmpMask,

102 int64_t &CmpValue) const override;

103

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108 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,

110

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123 unsigned &FalseOp, bool &Optimizable) const override;

124

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133

136 bool PreferFalse) const override;

137

140

145 int *BytesAdded = nullptr) const override;

146};

147

149 switch (Opcode) {

150 case Lanai::LDBs_RI:

151 case Lanai::LDBz_RI:

152 case Lanai::LDHs_RI:

153 case Lanai::LDHz_RI:

154 case Lanai::STB_RI:

155 case Lanai::STH_RI:

156 return true;

157 default:

158 return false;

159 }

160}

161

163 switch (Opcode) {

164 case Lanai::LDW_RI:

165 case Lanai::SW_RI:

166 return true;

167 default:

168 return false;

169 }

170}

171

173 switch (Opcode) {

174 case Lanai::LDBs_RR:

175 case Lanai::LDBz_RR:

176 case Lanai::LDHs_RR:

177 case Lanai::LDHz_RR:

178 case Lanai::LDWz_RR:

179 case Lanai::LDW_RR:

180 case Lanai::STB_RR:

181 case Lanai::STH_RR:

182 case Lanai::SW_RR:

183 return true;

184 default:

185 return false;

186 }

187}

188

189}

190

191#endif

unsigned const MachineRegisterInfo * MRI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef< MachineOperand > Condition, const DebugLoc &DL, int *BytesAdded=nullptr) const override

bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl< MachineOperand > &Condition, bool AllowModify) const override

virtual const LanaiRegisterInfo & getRegisterInfo() const

Definition LanaiInstrInfo.h:36

MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool PreferFalse) const override

bool expandPostRAPseudo(MachineInstr &MI) const override

LanaiInstrInfo(const LanaiSubtarget &STI)

bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Condition) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, Register DestinationRegister, Register SourceRegister, bool KillSource, bool RenamableDest=false, bool RenamableSrc=false) const override

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

This is an optimization pass for GlobalISel generic memory operations.

static bool isRMOpcode(unsigned Opcode)

Definition LanaiInstrInfo.h:162

static bool isRRMOpcode(unsigned Opcode)

Definition LanaiInstrInfo.h:172

static bool isSPLSOpcode(unsigned Opcode)

Definition LanaiInstrInfo.h:148