LanaiRegisterInfo.cpp Source File (original) (raw)

27#define GET_REGINFO_TARGET_DESC

28#include "LanaiGenRegisterInfo.inc"

30using namespace llvm;

36 return CSR_SaveList;

37}

67 switch (Opcode) {

68 case Lanai::ADD_I_LO:

69 case Lanai::SUB_I_LO:

70 case Lanai::ADD_F_I_LO:

71 case Lanai::SUB_F_I_LO:

72 case Lanai::ADDC_I_LO:

73 case Lanai::SUBB_I_LO:

74 case Lanai::ADDC_F_I_LO:

75 case Lanai::SUBB_F_I_LO:

76 return true;

77 default:

78 return false;

79 }

80}

83 switch (Opcode) {

84 case Lanai::ADD_I_LO:

85 return Lanai::SUB_I_LO;

86 case Lanai::SUB_I_LO:

87 return Lanai::ADD_I_LO;

88 case Lanai::ADD_F_I_LO:

89 return Lanai::SUB_F_I_LO;

90 case Lanai::SUB_F_I_LO:

91 return Lanai::ADD_F_I_LO;

92 case Lanai::ADDC_I_LO:

93 return Lanai::SUBB_I_LO;

94 case Lanai::SUBB_I_LO:

95 return Lanai::ADDC_I_LO;

96 case Lanai::ADDC_F_I_LO:

97 return Lanai::SUBB_F_I_LO;

98 case Lanai::SUBB_F_I_LO:

99 return Lanai::ADDC_F_I_LO;

100 default:

102 }

103}

104

106 switch (Opcode) {

107 case Lanai::LDBs_RI:

108 return Lanai::LDBs_RR;

109 case Lanai::LDBz_RI:

110 return Lanai::LDBz_RR;

111 case Lanai::LDHs_RI:

112 return Lanai::LDHs_RR;

113 case Lanai::LDHz_RI:

114 return Lanai::LDHz_RR;

115 case Lanai::LDW_RI:

116 return Lanai::LDW_RR;

117 case Lanai::STB_RI:

118 return Lanai::STB_RR;

119 case Lanai::STH_RI:

120 return Lanai::STH_RR;

121 case Lanai::SW_RI:

122 return Lanai::SW_RR;

123 default:

125 }

126}

127

129 int SPAdj, unsigned FIOperandNum,

131 assert(SPAdj == 0 && "Unexpected");

132

137 bool HasFP = TFI->hasFP(MF);

139

140 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();

141

143 MI.getOperand(FIOperandNum + 1).getImm();

144

145

146

147 if (!HasFP || (hasStackRealignment(MF) && FrameIndex >= 0))

149

151 if (FrameIndex >= 0) {

154 else if (hasStackRealignment(MF))

155 FrameReg = Lanai::SP;

156 }

157

158

159

160

161

164 assert(RS && "Register scavenging must be on");

165 Register Reg = RS->FindUnusedReg(&Lanai::GPRRegClass);

166 if (!Reg)

167 Reg = RS->scavengeRegisterBackwards(Lanai::GPRRegClass, II, false, SPAdj);

168 assert(Reg && "Register scavenger failed");

169

170 bool HasNegOffset = false;

171

172

174 HasNegOffset = true;

176 }

177

179

180 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::MOVHI), Reg)

182 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::OR_I_LO), Reg)

185 } else {

186

187 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::ADD_I_LO), Reg)

190 }

191

192 if (MI.getOpcode() == Lanai::ADD_I_LO) {

194 HasNegOffset ? TII->get(Lanai::SUB_R) : TII->get(Lanai::ADD_R),

195 MI.getOperand(0).getReg())

199 MI.eraseFromParent();

200 return true;

201 }

204 if (HasNegOffset) {

205

206

208 "Unexpected ALU op in RRM instruction");

210 }

211 } else

212 llvm_unreachable("Unexpected opcode in frame index operation");

213

214 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);

215 MI.getOperand(FIOperandNum + 1)

216 .ChangeToRegister(Reg, false, false,

217 true);

218 return false;

219 }

220

221

222

223

226

227

228

229

231 MI.getOperand(0).getReg())

234 MI.eraseFromParent();

235 return true;

236 }

237

238 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);

239 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);

240 return false;

241}

242

245

246

248 return true;

249

250 return false;

251}

252

254

257 return Lanai::FP;

258}

259

261

265 return CSR_RegMask;

266}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file implements the BitVector class.

static unsigned getRRMOpcodeVariant(unsigned Opcode)

Definition LanaiRegisterInfo.cpp:105

static bool isALUArithLoOpcode(unsigned Opcode)

Definition LanaiRegisterInfo.cpp:66

static unsigned getOppositeALULoOpcode(unsigned Opcode)

Definition LanaiRegisterInfo.cpp:82

uint64_t IntrinsicInst * II

This file declares the machine register scavenger class.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool hasVarSizedObjects() const

This method may be called any time after instruction selection is complete to determine if the stack ...

uint64_t getStackSize() const

Return the number of bytes that must be allocated to hold all of the fixed size frame objects.

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

Information about stack frame layout on the target.

bool hasFP(const MachineFunction &MF) const

hasFP - Return true if the specified function should have a dedicated frame pointer register.

TargetInstrInfo - Interface to description of machine instruction set.

virtual const TargetFrameLowering * getFrameLowering() const

virtual const TargetInstrInfo * getInstrInfo() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

static bool isRMOpcode(unsigned Opcode)

static bool isSPLSOpcode(unsigned Opcode)

LanaiRegisterInfo()

Definition LanaiRegisterInfo.cpp:32

Definition LanaiRegisterInfo.cpp:260

unsigned getRARegister() const

Definition LanaiRegisterInfo.cpp:253

bool hasBasePointer(const MachineFunction &MF) const

Definition LanaiRegisterInfo.cpp:243

bool requiresRegisterScavenging(const MachineFunction &MF) const override

Definition LanaiRegisterInfo.cpp:61

const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=nullptr) const override

Definition LanaiRegisterInfo.cpp:35

const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override

Definition LanaiRegisterInfo.cpp:263

bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

Definition LanaiRegisterInfo.cpp:128

Definition LanaiRegisterInfo.cpp:256

BitVector getReservedRegs(const MachineFunction &MF) const override

Definition LanaiRegisterInfo.cpp:39