LiveRegMatrix.cpp Source File (original) (raw)

29#include

31using namespace llvm;

33#define DEBUG_TYPE "regalloc"

35 STATISTIC(NumAssigned , "Number of registers assigned");

36 STATISTIC(NumUnassigned , "Number of registers unassigned");

40 "Live Register Matrix", false, false)

47 AU.setPreservesAll();

51}

56 LRM.init(MF, LIS, VRM);

57 return false;

58}

63 LIS = &pLIS;

64 VRM = &pVRM;

66 unsigned NumRegUnits = TRI->getNumRegUnits();

67 if (NumRegUnits != Matrix.size())

69 Matrix.init(*LIUAlloc, NumRegUnits);

73}

77void LiveRegMatrix::releaseMemory() {

78 for (unsigned i = 0, e = Matrix.size(); i != e; ++i) {

79 Matrix[static_cast<MCRegUnit>(i)].clear();

83 }

84}

86template

89 Callable Func) {

92 MCRegUnit Unit = (*Units).first;

95 if ((S.LaneMask & Mask).any()) {

96 if (Func(Unit, S))

97 return true;

98 break;

99 }

100 }

101 }

102 } else {

103 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {

104 if (Func(Unit, VRegInterval))

105 return true;

106 }

107 }

108 return false;

109}

110

113 << printReg(PhysReg, TRI) << ':');

114 assert(!VRM->hasPhys(VirtReg.reg()) && "Duplicate VirtReg assignment");

115 VRM->assignVirt2Phys(VirtReg.reg(), PhysReg);

116

118 TRI, VirtReg, PhysReg, [&](MCRegUnit Unit, const LiveRange &Range) {

120 Matrix[Unit].unify(VirtReg, Range);

121 return false;

122 });

123

124 ++NumAssigned;

126}

127

129 Register PhysReg = VRM->getPhys(VirtReg.reg());

131 << " from " << printReg(PhysReg, TRI) << ':');

132 VRM->clearVirt(VirtReg.reg());

133

137 Matrix[Unit].extract(VirtReg, Range);

138 return false;

139 });

140

141 ++NumUnassigned;

143}

144

146 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {

147 if (!Matrix[Unit].empty())

148 return true;

149 }

150 return false;

151}

152

155

156

157

158 if (RegMaskVirtReg != VirtReg.reg() || RegMaskTag != UserTag) {

159 RegMaskVirtReg = VirtReg.reg();

160 RegMaskTag = UserTag;

161 RegMaskUsable.clear();

162 LIS->checkRegMaskInterference(VirtReg, RegMaskUsable);

163 }

164

165

166

167

168 return !RegMaskUsable.empty() &&

169 (!PhysReg || !RegMaskUsable.test(PhysReg.id()));

170}

171

174 if (VirtReg.empty())

175 return false;

177

179 TRI, VirtReg, PhysReg, [&](MCRegUnit Unit, const LiveRange &Range) {

180 const LiveRange &UnitRange = LIS->getRegUnit(Unit);

181 return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes());

182 });

183 return Result;

184}

185

187 MCRegUnit RegUnit) {

189 Q.init(UserTag, LR, Matrix[RegUnit]);

190 return Q;

191}

192

196 if (VirtReg.empty())

198

199

202

203

206

207

208 bool Interference = foreachUnit(TRI, VirtReg, PhysReg,

209 [&](MCRegUnit Unit, const LiveRange &LR) {

211 });

212 if (Interference)

214

216}

217

220

221 VNInfo valno(0, Start);

225

226

227 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {

228

229

230

231

232

233

234

235

236

237

238

239

241 Q.reset(UserTag, LR, Matrix[Unit]);

243 return true;

244 }

245 return false;

246}

247

251

252 VNInfo valno(0, Start);

256

258

259

261 auto [Unit, Lanes] = *MCRU;

262

263

264

265

266

267

268

269

270

271

272

273

275 Q.reset(UserTag, LR, Matrix[Unit]);

277 InterferingLanes |= Lanes;

278 }

279

280 return InterferingLanes;

281}

282

285 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {

286 if ((VRegInterval = Matrix[Unit].getOneVReg()))

287 return VRegInterval->reg();

288 }

289

291}

292

294

300 LRM.init(MF, LIS, VRM);

301 return LRM;

302}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

A common definition of LaneBitmask for use in TableGen and CodeGen.

Live Register Matrix

Definition LiveRegMatrix.cpp:44

static bool foreachUnit(const TargetRegisterInfo *TRI, const LiveInterval &VRegInterval, MCRegister PhysReg, Callable Func)

Definition LiveRegMatrix.cpp:87

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

A helper class for register coalescers.

Query interferences between a single live virtual register and a live interval union.

void init(unsigned NewUserTag, const LiveRange &NewLR, const LiveIntervalUnion &NewLiveUnion)

void reset(unsigned NewUserTag, const LiveRange &NewLR, const LiveIntervalUnion &NewLiveUnion)

A live range for subregisters.

LiveInterval - This class represents the liveness of a register, or stack slot.

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

This class represents the liveness of a register, stack slot, etc.

LLVM_ABI iterator addSegment(Segment S)

Add the specified Segment to this range, merging segments as appropriate.

LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition LiveRegMatrix.cpp:295

void releaseMemory() override

releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...

Definition LiveRegMatrix.cpp:75

LiveRegMatrixWrapperLegacy()

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...

Definition LiveRegMatrix.cpp:46

bool runOnMachineFunction(MachineFunction &MF) override

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

Definition LiveRegMatrix.cpp:53

bool checkRegMaskInterference(const LiveInterval &VirtReg, MCRegister PhysReg=MCRegister::NoRegister)

Check for regmask interference only.

Definition LiveRegMatrix.cpp:153

void unassign(const LiveInterval &VirtReg)

Unassign VirtReg from its PhysReg.

Definition LiveRegMatrix.cpp:128

bool isPhysRegUsed(MCRegister PhysReg) const

Returns true if the given PhysReg has any live intervals assigned.

Definition LiveRegMatrix.cpp:145

void invalidateVirtRegs()

Invalidate cached interference queries after modifying virtual register live ranges.

Definition LiveRegMatrix.cpp:283

LiveIntervalUnion::Query & query(const LiveRange &LR, MCRegUnit RegUnit)

Query a line of the assigned virtual register matrix directly.

Definition LiveRegMatrix.cpp:186

@ IK_VirtReg

Virtual register interference.

@ IK_RegUnit

@ IK_Free

No interference, go ahead and assign.

@ IK_RegMask

RegMask interference.

void init(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM)

Definition LiveRegMatrix.cpp:60

void assign(const LiveInterval &VirtReg, MCRegister PhysReg)

Assign VirtReg to PhysReg.

Definition LiveRegMatrix.cpp:111

InterferenceKind checkInterference(const LiveInterval &VirtReg, MCRegister PhysReg)

Check for interference before assigning VirtReg to PhysReg.

Definition LiveRegMatrix.cpp:194

bool checkRegUnitInterference(const LiveInterval &VirtReg, MCRegister PhysReg)

Check for regunit interference only.

Definition LiveRegMatrix.cpp:172

LaneBitmask checkInterferenceLanes(SlotIndex Start, SlotIndex End, MCRegister PhysReg)

Check for interference in the segment [Start, End) that may prevent assignment to PhysReg,...

Definition LiveRegMatrix.cpp:248

MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.

bool isValid() const

Returns true if this iterator is not yet at the end.

Wrapper class representing physical registers. Should be passed by value.

static constexpr unsigned NoRegister

constexpr unsigned id() const

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

AnalysisType & getAnalysis() const

getAnalysis() - This function is used by subclasses to get to the analysis information ...

Wrapper class representing virtual and physical registers.

SlotIndex - An opaque wrapper around machine indexes.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

VNInfo - Value Number Information.

LLVM_ABI void init(MachineFunction &MF)

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI Printable printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI)

Create Printable object to print register units on a raw_ostream.

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

A special type used by analysis passes to provide an address that identifies that particular analysis...

This represents a simple continuous liveness interval for a value.