LiveRegMatrix.cpp Source File (original) (raw)

29#include

31using namespace llvm;

33#define DEBUG_TYPE "regalloc"

35 STATISTIC(NumAssigned , "Number of registers assigned");

36 STATISTIC(NumUnassigned , "Number of registers unassigned");

40 "Live Register Matrix", false, false)

47 AU.setPreservesAll();

51}

54 auto &LIS = getAnalysis().getLIS();

55 auto &VRM = getAnalysis().getVRM();

56 LRM.init(MF, LIS, VRM);

57 return false;

58}

63 LIS = &pLIS;

64 VRM = &pVRM;

67 if (NumRegUnits != Matrix.size())

69 Matrix.init(*LIUAlloc, NumRegUnits);

73}

77void LiveRegMatrix::releaseMemory() {

78 for (unsigned i = 0, e = Matrix.size(); i != e; ++i) {

79 Matrix[i].clear();

83 }

84}

86template

89 Callable Func) {

92 unsigned Unit = (*Units).first;

95 if ((S.LaneMask & Mask).any()) {

96 if (Func(Unit, S))

97 return true;

98 break;

99 }

100 }

101 }

102 } else {

103 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {

104 if (Func(Unit, VRegInterval))

105 return true;

106 }

107 }

108 return false;

109}

110

113 << printReg(PhysReg, TRI) << ':');

114 assert(!VRM->hasPhys(VirtReg.reg()) && "Duplicate VirtReg assignment");

116

118 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) {

120 Matrix[Unit].unify(VirtReg, Range);

121 return false;

122 });

123

124 ++NumAssigned;

126}

127

131 << " from " << printReg(PhysReg, TRI) << ':');

133

137 Matrix[Unit].extract(VirtReg, Range);

138 return false;

139 });

140

141 ++NumUnassigned;

143}

144

147 if (!Matrix[Unit].empty())

148 return true;

149 }

150 return false;

151}

152

155

156

157

158 if (RegMaskVirtReg != VirtReg.reg() || RegMaskTag != UserTag) {

159 RegMaskVirtReg = VirtReg.reg();

160 RegMaskTag = UserTag;

161 RegMaskUsable.clear();

163 }

164

165

166

167

168 return !RegMaskUsable.empty() &&

169 (!PhysReg || !RegMaskUsable.test(PhysReg.id()));

170}

171

174 if (VirtReg.empty())

175 return false;

177

178 bool Result = foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,

182 });

183 return Result;

184}

185

189 Q.init(UserTag, LR, Matrix[RegUnit]);

190 return Q;

191}

192

196 if (VirtReg.empty())

198

199

202

203

206

207

208 bool Interference = foreachUnit(TRI, VirtReg, PhysReg,

211 });

212 if (Interference)

214

216}

217

220

221 VNInfo valno(0, Start);

225

226

228

229

230

231

232

233

234

235

236

237

238

239

241 Q.reset(UserTag, LR, Matrix[Unit]);

243 return true;

244 }

245 return false;

246}

247

251

252 VNInfo valno(0, Start);

256

258

259

261 auto [Unit, Lanes] = *MCRU;

262

263

264

265

266

267

268

269

270

271

272

273

275 Q.reset(UserTag, LR, Matrix[Unit]);

277 InterferingLanes |= Lanes;

278 }

279

280 return InterferingLanes;

281}

282

286 if ((VRegInterval = Matrix[Unit].getOneVReg()))

287 return VRegInterval->reg();

288 }

289

291}

292

294

300 LRM.init(MF, LIS, VRM);

301 return LRM;

302}

Looks at all the uses of the given value Returns the Liveness deduced from the uses of this value Adds all uses that cause the result to be MaybeLive to MaybeLiveRetUses If the result is Live

A common definition of LaneBitmask for use in TableGen and CodeGen.

static bool foreachUnit(const TargetRegisterInfo *TRI, const LiveInterval &VRegInterval, MCRegister PhysReg, Callable Func)

unsigned const TargetRegisterInfo * TRI

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

A container for analyses that lazily runs them and caches their results.

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

bool test(unsigned Idx) const

void clear()

clear - Removes all bits from the bitvector.

bool empty() const

empty - Tests whether there are no bits in this bitvector.

A helper class for register coalescers.

void init(LiveIntervalUnion::Allocator &, unsigned Size)

Query interferences between a single live virtual register and a live interval union.

void init(unsigned NewUserTag, const LiveRange &NewLR, const LiveIntervalUnion &NewLiveUnion)

void reset(unsigned NewUserTag, const LiveRange &NewLR, const LiveIntervalUnion &NewLiveUnion)

A live range for subregisters.

LiveInterval - This class represents the liveness of a register, or stack slot.

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

bool checkRegMaskInterference(const LiveInterval &LI, BitVector &UsableRegs)

Test if LI is live across any register mask instructions, and compute a bit mask of physical register...

SlotIndexes * getSlotIndexes() const

LiveRange & getRegUnit(unsigned Unit)

Return the live range for register unit Unit.

This class represents the liveness of a register, stack slot, etc.

iterator addSegment(Segment S)

Add the specified Segment to this range, merging segments as appropriate.

LiveRegMatrix run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

void releaseMemory() override

releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...

bool runOnMachineFunction(MachineFunction &MF) override

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

bool checkRegMaskInterference(const LiveInterval &VirtReg, MCRegister PhysReg=MCRegister::NoRegister)

Check for regmask interference only.

void unassign(const LiveInterval &VirtReg)

Unassign VirtReg from its PhysReg.

bool isPhysRegUsed(MCRegister PhysReg) const

Returns true if the given PhysReg has any live intervals assigned.

void invalidateVirtRegs()

Invalidate cached interference queries after modifying virtual register live ranges.

LiveIntervalUnion::Query & query(const LiveRange &LR, MCRegUnit RegUnit)

Query a line of the assigned virtual register matrix directly.

@ IK_VirtReg

Virtual register interference.

@ IK_RegUnit

@ IK_Free

No interference, go ahead and assign.

@ IK_RegMask

RegMask interference.

void init(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM)

void assign(const LiveInterval &VirtReg, MCRegister PhysReg)

Assign VirtReg to PhysReg.

InterferenceKind checkInterference(const LiveInterval &VirtReg, MCRegister PhysReg)

Check for interference before assigning VirtReg to PhysReg.

bool checkRegUnitInterference(const LiveInterval &VirtReg, MCRegister PhysReg)

Check for regunit interference only.

LaneBitmask checkInterferenceLanes(SlotIndex Start, SlotIndex End, MCRegister PhysReg)

Check for interference in the segment [Start, End) that may prevent assignment to PhysReg,...

MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.

bool isValid() const

Returns true if this iterator is not yet at the end.

unsigned getNumRegUnits() const

Return the number of (native) register units in the target.

iterator_range< MCRegUnitIterator > regunits(MCRegister Reg) const

Returns an iterator range over all regunits for Reg.

Wrapper class representing physical registers. Should be passed by value.

static constexpr unsigned NoRegister

constexpr unsigned id() const

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Wrapper class representing virtual and physical registers.

SlotIndex - An opaque wrapper around machine indexes.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

VNInfo - Value Number Information.

void clearVirt(Register virtReg)

clears the specified virtual register's, physical register mapping

void assignVirt2Phys(Register virtReg, MCRegister physReg)

creates a mapping for the specified virtual register to the specified physical register

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

bool hasPhys(Register virtReg) const

returns true if the specified virtual register is mapped to a physical register

This is an optimization pass for GlobalISel generic memory operations.

Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)

Create Printable object to print register units on a raw_ostream.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

A special type used by analysis passes to provide an address that identifies that particular analysis...

This represents a simple continuous liveness interval for a value.